2011
DOI: 10.1007/978-3-642-22453-9_40
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On Approximate Reduction of Multi-Port Resistor Networks

Abstract: Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28-39, 2010) The novelty in our approach is that we obtain improved reductions, by developing error estimations… Show more

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Cited by 1 publication
(2 citation statements)
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“…Thus, for a given , resistors satisfying (8) can be deleted. From a practical point of view, estimation (7) is not sharp and does not deliver significant improvements in sparsity neither for original nor for reduced resistor networks [7]. In Section 4, we will derive a different estimation for (6), which is sharp and cheap to compute.…”
Section: Simplification Of Resistor Networkmentioning
confidence: 99%
See 1 more Smart Citation
“…Thus, for a given , resistors satisfying (8) can be deleted. From a practical point of view, estimation (7) is not sharp and does not deliver significant improvements in sparsity neither for original nor for reduced resistor networks [7]. In Section 4, we will derive a different estimation for (6), which is sharp and cheap to compute.…”
Section: Simplification Of Resistor Networkmentioning
confidence: 99%
“…In this section, we suggest an error estimation for the maximum relative error of vector of voltages that shows to be much more sharp than the error estimation based on the condition number (7). In order to derive it, we consider…”
Section: Error Estimation For Jjv Q Vjj Jjvjjmentioning
confidence: 99%