On area/depth trade-off in LUT-based FPGA technology mapping

Abstract

In this paper, we study the area and depth tradeoff in lookup-table (LUT) based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a sequence of depth relaxation operations and area-minimizing mapping procedures to produce a set of mapping solutions for a given design with smooth area and depth trade-off. As the core of the area minimization step, we have developed a polynomial time optimal algorithm for computing an area-minimum mapping solution without node duplication for a K-bounded general Boolean network, which makes a significant step towards complete understanding of the general area minimization problem in FPGA technology mapping. The experimental results on MCNC benchmark circuits show that our solution sets outperform the solutions produced by most existing mapping algorithms in terms of both area and depth minimization.

Power-aware technology mapping for LUT-based FPGAs

“…We compare our technology mapper with two publicly available technology mappers: 1) FlowMap [4], which maps circuits in a depth-optimal manner and 2) FlowMap-r [5], which optimizes both depth and area by relaxing the depth optimality on portions of a circuit that are not depthcritical and then performing duplication-free mapping. Additionally, we consider the effect of using various areareducing post-processing routines, including FlowPack (FP) [4], MP-Pack (MP) 1 [15].…”

“…An important step in the FPGA CAD flow is technology mapping, which involves transforming a circuit from a generic form into a network of LUTs. LUT-based technology mapping has been studied extensively in recent years, with most research being focused on optimizing the area [3] and/or the depth [4,5] of the mapped circuit. Power represents the third, largely unexplored axis along which an FPGA design should be optimized.…”

Smart Enumeration: A Systematic Approach to Exhaustive Search

“…Cong et al concentrate on enumeration of single output, K-input connected subgraphs (fanout-free cones) within the circuit, and prove that the problem can still be optimally solved by decomposing the circuit into maximal fanout-free cones (MFFC), and enumerating separately on each MFFC [3]. The proposed algorithm restricts the solution to duplication-free mappings where each circuit gate must be mapped to exactly one LUT.…”

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

“…The most dramatic case is the mapping results of the benchmark circuit e64 in which the levels of mapping results produced by our algorithm vary from 17 to 3. Table III shows the comparisons between the results produced by our algorithm, denoted as ALTO (stands for Area/Level Trade-Off), with those produced by another area/level trade-off algorithm named FlowMap-r [13], denoted FM-r. For most of the benchmark circuits, the mapping solutions of ALTO outperform those of FlowMap-r on the same level.…”

“…An algorithm, named FlowMap-r, has been proposed to provide this capability [13]. It starts from a level-optimal mapping solution produced by FlowMap [11].…”