On automatic software-based self-test program generation based on high-level decision diagrams

Jasnetski, Artjom; Ubar, Raimund; Tsertov, Anton

doi:10.1109/latw.2016.7483357

Cited by 6 publications

(3 citation statements)

References 3 publications

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“…[23] describes how to derive test patterns intended for online testing starting from programs originally intended for verification purposes, significantly increasing the final coverage of stuckat faults on a RISCV core. Works [24], [25], on the other hand, present a tool based on High-Level Decision Diagrams (HLDDs) for modeling microprocessors and faults, used in conjunction with previously prepared code templates to generate the final self-test program targeting stuck-at faults. These works show that methodologies for improving test programs can be successfully devised.…”

Section: B Related Workmentioning

confidence: 99%

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries

Cantoro

Garau

Girard

et al. 2022

2022 IEEE European Test Symposium (ETS)

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In-field test of integrated circuits using Self-Test Libraries (STLs) is a widely used technique specifically suited to guarantee the processor's correct behavior during the operative lifetime, as mandated by functional safety standards such as ISO26262. Developing STLs for stuck-at faults requires significant manual efforts from test engineers, and targeting delay faults is even more challenging. In order to support this process, in this paper we propose a method to automate the creation of STLs targeting delay faults starting from existing STLs targeting stuck-at faults. The method is based first on identifying excited but not-observed transition delay faults and then adding suitable instructions able to observe (and hence detect) them. Experimental results on a RISC-V processor show that the method can systematically detect a significant percentage of the target faults with reasonable computational effort and test code size increase.

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Section: B Related Workmentioning

confidence: 99%

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries

Cantoro

Garau

Girard

et al. 2022

2022 IEEE European Test Symposium (ETS)

View full text Add to dashboard Cite

show abstract

“…[22] describes how to derive test patterns for online testing starting from programs originally intended for verification purposes, significantly increasing the final coverage of stuck-at faults on a RISCV core. Works [23], [24] present a tool based on High-Level Decision Diagrams for modeling microprocessors and faults, used in conjunction with previously prepared code templates to generate the final self-test program. These works show that methodologies for improving test programs, although tailored for SAFs, can be successfully devised.…”

Section: Introductionmentioning

confidence: 99%

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

Cantoro

Girard

Masante

et al. 2021

2021 IEEE 27th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Testing digital integrated circuits is generally done using Design-for-Testability (DfT) solutions. Such solutions, however, introduce non-negligible area and timing overheads that can be overcome by adopting functional solutions. In particular, functional test of integrated circuits plays a key role when guaranteeing the device's safety is required during the operative lifetime (in-field test), as required by standards like ISO26262. This can be achieved via the execution of a Self-Test Library (STL) by the device under test (DUT). Nevertheless, developing such test programs requires a significant manual effort, and can be non-trivial when dealing with complex modules. This paper moves the first step in defining a generic and systematic methodology to improve transition delay faults' observability of existing STLs. To do so, we analyze previously devised STLs in order to highlight specific points within test programs to be improved, leading to an increase in the final fault coverage.

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“…A test generation method has been proposed in [12] which is capable of producing test programs having a low number of test instructions and an acceptable fault coverage for complex processors. An automatic method based on high-level decision diagrams has been proposed in [13] which is capable of producing a test program for a processor only by receiving the instruction set of that processor as an input.…”

Section: Introductionmentioning

confidence: 99%

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Kamran

2019

IET Computers & Digital Techniques

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In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors' results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

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On automatic software-based self-test program generation based on high-level decision diagrams

Cited by 6 publications

References 3 publications

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

HASTI: hardware‐assisted functional testing of embedded processors in idle times

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