On-board inertial-assisted visual odometer on an embedded system

Zhou, Guyue; Ye, Jiaxin; Ren, Wei; Wang, Tao; Li, Zigang

doi:10.1109/icra.2014.6907232

Cited by 19 publications

(14 citation statements)

References 14 publications

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“…The reported update rate is about 20 frames per second for images with the resolution of 752×480 pixels. Similar results with a slightly different approach are presented in [19].…”

Section: Related Worksupporting

confidence: 74%

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On Fpga Based Acceleration of Image Processing in Mobile Robotics

Petr

Faigl

2015

APP

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Abstract. In visual navigation tasks, a lack of the computational resources is one of the main limitations of micro robotic platforms to be deployed in autonomous missions. It is because the most of nowadays techniques of visual navigation relies on a detection of salient points that is computationally very demanding. In this paper, an FPGA assisted acceleration of image processing is considered to overcome limitations of computational resources available on-board and to enable high processing speeds while it may lower the power consumption of the system. The paper reports on performance evaluation of the CPU-based and FPGA-based implementations of a visual teach-and-repeat navigation system based on detection and tracking of the FAST image salient points. The results indicate that even a computationally efficient FAST algorithm can benefit from a parallel (low-cost) FPGA-based implementation that has a competitive processing time but more importantly it is a more power efficient.

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“…The reported update rate is about 20 frames per second for images with the resolution of 752×480 pixels. Similar results with a slightly different approach are presented in [19].…”

Section: Related Worksupporting

confidence: 74%

“…However, the most promising are the approaches ( [17][18][19][20]) based on the FAST feature detector [6] because this detector is widely adopted by the robotic community due to its low computational complexity. Hence, it represents a base for further methods.…”

Section: Related Workmentioning

confidence: 99%

On Fpga Based Acceleration of Image Processing in Mobile Robotics

Petr

Faigl

2015

APP

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“…Hardware and Software Co-design 1) System Overview: This work is in fact an updated version of our previous work [10] therefore a low-cost Altera SoC FPGA (with ARM hardcores inside) continues to be selected as the main processor with the following advantages.…”

Section: A Sensor Con¿gurationsmentioning

confidence: 99%

“…The obtained feature information and dense depth map will go back to DDR for buffering. Interested readers can refer to [10] for some module-level details for FPGA implementation. Finally, the ARM hardcore will convert the collected data from multiple sensors to visual mapping results recorded in a SD card according to the green data Àow in Fig.…”

Section: A Sensor Con¿gurationsmentioning

confidence: 99%

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An Embedded Solution to Visual Mapping for Consumer Drones

Zhou

Liu

Yang³

et al. 2014

2014 IEEE Conference on Computer Vision and Pattern Recognition Workshops

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In this paper, we propose a real-time visual mapping scheme which can be implemented on a low-cost embedded system for consumer-level ratio control (RC) drones. In our work, a 3-dimensional occupancy grid map is obtained based on an estimated trajectory from data fusion of multiple on-board sensors, composed of two downward-facing cameras, two forward-facing cameras, a GPS receiver, a magnetic compass and an inertial measurement unit (IMU) with 3-axis accelerometers and gyroscopes. Taking the advantages of the low-cost FPGA and ARM NEON intrinsics, we run our visual odometry and mapping algorithms at 10Hz on board. Meanwhile, we also present a hierarchical multi-sensor fusion algorithm to provide a robust trajectory for mapping usage. Finally, we verify the feasibility of our approaches and serval potential applications with experimental results in complex indoor/outdoor environments.

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FPGA‐SoC implementation of an ICA‐based background subtraction method

Carrizosa-Corral

Vázquez-Cervantes

Montes

et al. 2018

Circuit Theory & Apps

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SummaryThis paper presents the development and implementation of an independent component analysis (ICA)–based background subtraction method on a field programmable gate array (FPGA) system on a chip (SoC) with embedded processor. The use of the classic form of ICA for this purpose results in a complex implementation with high hardware resource usage for an embedded system. Therefore, an alternative version of FastICA was developed that adapts directly to the parallelism offered by the FPGA. In addition, the incorporation of this version of ICA into the motion‐detection method exploits the architecture of the FPGA‐SoC with embedded processor. This recent technology complements the parallelism of the FPGA with the general‐purpose computing capacity of the processors while maintaining low energy consumption and a compact size. The above features are appropriate for autonomous devices that handle mainly background subtraction, while a central device receives this information and performs the remaining tasks required for the application. The use of processors allows a faster implementation and integration of the device into other systems in a simple manner, while the parallelism of the FPGA increases the processing speed by accelerating intensive numeric calculations. The results obtained from the implementation that uses both FPGA and the embedded processor of the SoC show an increase of 3300% in the number of frames per second compared with an implementation that uses only the embedded processor.

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On-board inertial-assisted visual odometer on an embedded system

Cited by 19 publications

References 14 publications

On Fpga Based Acceleration of Image Processing in Mobile Robotics

On Fpga Based Acceleration of Image Processing in Mobile Robotics

An Embedded Solution to Visual Mapping for Consumer Drones

FPGA‐SoC implementation of an ICA‐based background subtraction method

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