On-Chip Adaptive VDD Scaled Architecture of Reliable SRAM Cell With Improved Soft Error Tolerance

Gupta, Neha; Shah, Ambika Prasad; Kumar, Rana Sagar; Gupta, Tanisha; Khan, Sajid; Vishvakarma, Santosh Kumar

doi:10.1109/tdmr.2020.3019135

Cited by 6 publications

(12 citation statements)

References 35 publications

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“…Soft error rate is calculated for different latches as compared to the reference unhardened latch (RL) at different supply voltage and temperature conditions. The soft error rate ratio (SERR) is calculated to analyze the soft error rate (SER) of the considered latches normalized to the reference latch (SER 𝑅𝐿 ) [2]. Therefore, the SERR is calculated using the given equation:…”

Section: Soft Error Rate Ratiomentioning

confidence: 99%

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits

Gupta

Amesur

Dhakad

et al. 2021

Proceedings of the 2021 Great Lakes Symposium on VLSI

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Soft error is one of the major reliability issue with technology scaling. In this work, we propose a radiation hardened voltage bootstrapped schmitt trigger (VB-ST) latch. To evaluate the circuit radiation resilience, we calculated the critical charge under the PVT variations at the most sensitive node and observed that the proposed latch has the highest critical charge and the lowest soft error rate ratio when compared to existing latches. We analyzed the impact of process variations on our design and observed that the VB-ST latch has 0.42× less critical voltage variability as compared to ST latch. Further, dynamic power and propagation delay are examined for various supply voltages, and we observed that the VB-ST latch has the lowest power consumption and delay propagation when compared to the other considered latches. For the validation of the proposed latch, a charge to power-delay-area product ratio (QPAR) is calculated and we clearly observed that the proposed VB-ST based latch significantly outperforms the performance of existing designs.

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Section: Soft Error Rate Ratiomentioning

confidence: 99%

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits

Gupta

Amesur

Dhakad

et al. 2021

Proceedings of the 2021 Great Lakes Symposium on VLSI

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“…However, the 6T cell has several unpreventable drawbacks such as read data disturbance, stability reduction at minimum supply voltage, considerable data retention voltage, half-select issue, and conflict of read and write operation [9]. Researchers have demonstrated many cell level or architecture level design approaches to resolve these issues such as read decoupled scheme [10,11], feedback cutting [12], single-ended approach [13,14], write assist technique [15], datadependent circuits [16,17], and stacking effects [18]. Hence, researchers aim to reduce the write power, read power, and leakage power while enhancing the read stability and write ability and resolving half-select issues [9].…”

Section: Introductionmentioning

confidence: 99%

“…The failure probability for the PFC10T cell is still considerably high in the read, write, and hold modes. The above-mentioned issues are resolved by a single SRAM cell named as a datadependent low power 10T SRAM cell [16,17] and is referred to as "D 2 LP10T" cell. Some performance parameters are evaluated in [16,17] and some additional parameters are analyzed in this work with the reference cells.…”

Section: Introductionmentioning

confidence: 99%

“…The above-mentioned issues are resolved by a single SRAM cell named as a datadependent low power 10T SRAM cell [16,17] and is referred to as "D 2 LP10T" cell. Some performance parameters are evaluated in [16,17] and some additional parameters are analyzed in this work with the reference cells. The D 2 LP10T cell can perform a successful operation even at considerably lower supply voltage (VDD = 0.4 V) and has almost negligible leakage power dissipation.…”

Section: Introductionmentioning

confidence: 99%

“…An error-tolerant and energy-efficient D 2 LP10T cell is referred from [16,17] for the IoT applications with improved stability and reduced leakage power consumption.…”

mentioning

confidence: 99%

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Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

et al. 2021

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This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

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One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

Darabi

Salehi

Abiri

2022

Circuit Theory & Apps

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This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime. The bit‐cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate‐wrap‐around (GWA) carbon nanotube (CNT)‐gate‐diffusion input (GDI) technique and only one‐bit line to perform both read and write operations to minimize active power consumption. The proposed bit‐cell uses a transmission gate network and write‐assist schemes to significantly improve the write‐ability and stack read‐decoupling technique to enhance hold‐/read‐stability. Moreover, a memory mini‐array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write‐ and read‐yield parameters for the proposed SRAM bit‐cell are about 22% and 13% better than counterpart bit‐cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit‐cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit‐cell in the real‐world application, a memory array architecture with an online (or off‐chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy‐efficient and noise‐immunity IoT platforms.

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On-Chip Adaptive VDD Scaled Architecture of Reliable SRAM Cell With Improved Soft Error Tolerance

Cited by 6 publications

References 35 publications

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

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