On chip high voltage single clock swing enhanced charge pump circuit in 0.18 &amp;#x00B5;m technology

Roushan, Rahul; Modak, Dipyaman; Mondal, Saroj; Paily, Roy

doi:10.1109/icpen.2012.6492341

Cited by 2 publications

(4 citation statements)

References 7 publications

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“…ISSCP is based on the same topology that was first used in [3] and later in [5]. ISSCP consists of three different blocks as shown in Fig.…”

Section: Enhanced Single-clock Charge Pumpmentioning

confidence: 99%

“…In our design, we have placed a buffer block which will incorporate these control circuitries. As the buffer is not designed, so for our experimental setup, we assumed that the buffer output voltage is a steady DC voltage V HIGH equals to the stable positive amplitude of the pulsating voltage V HIGHP as obtained from simulation results, this is based on the same logic that was used for SCSECP in [5].…”

Section: Enhanced Single-clock Charge Pumpmentioning

confidence: 99%

“…Ansari et al [4] proposed a single-clock charge pump circuit suitable for lowvoltage application. Roushan et al proposed a single-clock swing-enhanced charge pump (SCSECP) [5], which incorporates a single-clock charge pump and clocklevel shifter circuit to achieve higher output voltage. Recently, Mondal and Paliy proposed a new enhanced single-clock charge pump [6] suitable for micro-scale energy-harvesting systems.…”

Section: Introductionmentioning

confidence: 99%

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On-Chip Improved Single Clock Swing Enhanced Charge Pump Circuit

Deo

Roushan

Sah

2014

Advances in Intelligent Systems and Computing

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In this paper, an improved single-clock swing-enhanced charge pump circuit is presented. It is an improved version of single-clock swing-enhanced charge pump (SCSECP). We have made certain modifications in the previous SCSECP circuit while keeping the general topology same, and as a result, higher output voltage is achieved. In general, charge pump circuits use the available lowvoltage supply to generate a higher voltage, but in our case, the proposed six-stage charge pump gives an output voltage of 51.70 V at no-load for an input voltage of 1.2 V.

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“…ISSCP is based on the same topology that was first used in [3] and later in [5]. ISSCP consists of three different blocks as shown in Fig.…”

Section: Enhanced Single-clock Charge Pumpmentioning

confidence: 99%

Section: Enhanced Single-clock Charge Pumpmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On-Chip Improved Single Clock Swing Enhanced Charge Pump Circuit

Deo

Roushan

Sah

2014

Advances in Intelligent Systems and Computing

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“…Since the high voltage is supplied by onchip charge pump (CP) [2], the complicated operation voltage feature of eFlash memories [1,3] requires large area penalty of CP. Several designs of charge pump targeting smaller size and higher output capability have been proposed [3,4,5,6]. The issues of output ripple [4] and gate-oxide reliability [5] may become significant, or extra power dissipation, area occupation [6] and uneconomical process integration [3] are produced.…”

Section: Introductionmentioning

confidence: 99%

Area-efficient charge pump with local boost technique for embedded flash memory

Zhu

Jun

et al. 2017

IEICE Electron. Express

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An area-efficient charge pump (AE-CP) used for embedded flash memory is proposed with the combination of an area-efficient voltage doubler (AE-VD). An optimized strategy for AE-CP with local boost technique is discussed to maximize output capability by using low-voltage MOS capacitors together. The proposed circuits are simulated in a 130 nm CMOS process. Simulation results show the proposed AE-VD decreases the power consumption by 11.4%. And the proposed AE-CP with proposed voltage doubler achieves 29% improvement of the maximum output capability as compared to the conventional CP. A 253 × 8 KB embedded flash memory IP has been fabricated in HHGrace 130 nm 4 poly 4 metal CMOS process. The die size of the proposed IP is 0.65 mm 2 and the area size of charge pump has been reduced to 0.0317 mm 2 with an optimized α = 0.6 and the area ratio decreases by 10%.

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On chip high voltage single clock swing enhanced charge pump circuit in 0.18 µm technology

Cited by 2 publications

References 7 publications

On-Chip Improved Single Clock Swing Enhanced Charge Pump Circuit

On-Chip Improved Single Clock Swing Enhanced Charge Pump Circuit

Area-efficient charge pump with local boost technique for embedded flash memory

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