On-chip ID generation for multi-node implantable devices using SA-PUF

Gao, Chang; Ghoreishizadeh, Sara S.; Yan, Lianshan; Constandinou, Timothy G.

doi:10.1109/iscas.2017.8050422

Cited by 4 publications

(1 citation statement)

References 7 publications

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“…the fuse memory can be updated and used as address code). To further reduce the size and power of ID block, a dedicated low power physically unclonable function generator can be used, such as in [27] and [28] .…”

Section: Circuit Implementationmentioning

confidence: 99%

Four-Wire Interface ASIC for a Multi-Implant Link

Ghoreishizadeh

Haci

Liu

et al. 2017

IEEE Trans. Circuits Syst. I

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This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical “optrodes” that facilitate a bidirectional neural interface (electrical recording and optical stimulation), and the chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps), which is superimposed on a power carrier. On-chip power management provides an unregulated 5-V dc supply with up to 2.5-mA output current for stimulation, and two regulated voltages (3.3 and 3 V) with 60-dB power supply rejection ratio for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35-\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{upgreek} \usepackage{mathrsfs} \setlength{\oddsidemargin}{-69pt} \begin{document} }{}$\mu \text{m}$ \end{document} CMOS technology, occup-ying a 1.5-mm2 silicon area, and consumes a quiescent current of \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{upgreek} \usepackage{mathrsfs} \setlength{\oddsidemargin}{-69pt} \begin{document} }{}$91.2~\mu \text{A}$ \end{document}. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.

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Section: Circuit Implementationmentioning

confidence: 99%