On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

Liang, Joshua; Jalali, Mohammad Sadegh; Sheikholeslami, Ali; Kibune, Masaya; Tamura, Hirotaka

doi:10.1109/jssc.2014.2378280

Cited by 16 publications

(4 citation statements)

References 20 publications

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“…The degree of the eye margin degradation depends on the nature of the transmit jitter, the CDR gain, CDR bandwidth and its own jitter [27]. As such wireline transceiver designers have focused on characterizing and suppressing jitter for signal integrity purposes [28], [29]. In this work, it is ensured that these signal integrity considerations for high fidelity communications are maintained by message source driven equalization, and a parallel operation at the receiver extracts the transceiver jitter to be used for message source authentication.…”

Section: Jitter In Wireline Linksmentioning

confidence: 99%

Jitter-Based Authentication for Automotive Wireline Networks

Lang,

Musah

2024

IEEE Access

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This paper proposes a new authentication approach targeted to wireline broadcast communication systems for automotive and industrial applications. The proposed approach leverages jitter amplification in wireline channels, that become stronger features for messagesource authentication with higher data rate or channel loss, to provide a low-overhead physical layer authentication. The fundamentals of jitter amplification are reviewed and the use of it as a feature for authentication while maintaining high signal integrity is explored. Simulations using a Simulink model of an example automotive link with multiple electronic control units (ECUs) are used to show the efficacy of the proposed message source authentication scheme. The simulation results also show significant resilience of the proposed approach to noise. Measurement results using a bench-top setup show that the proposed feature detection approach has a high degree of authentication accuracy in a real-time application and provides a low-cost alternative to prevailing software-based approaches.

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Section: Jitter In Wireline Linksmentioning

confidence: 99%

Jitter-Based Authentication for Automotive Wireline Networks

Lang,

Musah

2024

IEEE Access

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“…In Fig. 5 to extract K E F F the following set of expressions from [9], [10] and [11] has been used in conjunction with the nonlinear simulation results:…”

Section: Dpc Modellingmentioning

confidence: 99%

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

Khanghah¹,

Sadeghipour²,

Kelly³

et al. 2022

IEEE Trans. Circuits Syst. I

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This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC's resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. Index Terms-Digital to phase converter (DPC), clock and data recovery (CDR), phase interpolator (PI), wireline and optical communication.

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“…A control register is used to program the different operation modes which include the calibration of the NT delay, the calibration of the delay lines, the selection of the measurement bin, and the operations of shifting data in and out for instrument programming and readout. This is facilitated by a standard 2.5 GHz 0.4 ps (1) 3.2 10 -3 130 nm [8] 0.82 GHz 0.031 ps 0.49 10 -3 65 nm [14] 5 GHz ≤1 ps 0.32 65 nm [5] 6 GHz 0.31 ps 15 10 -3 65 nm…”

Section: Time Difference Amplifiermentioning

confidence: 99%

A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology

Madhvaraj

Mir

Barragán

2022

2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)

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This paper describes an on-chip instrument for the estimation of absolute and period random jitter of clock signals in the GHz range with a sub-picosecond resolution. A selfreferenced technique is used to remove the need of a very clean external reference clock. The instrument has been designed in STMicroelectronics 28 nm FDSOI technology. By exploiting the fine delay control which can be achieved with this technology, simulation results haven shown a resolution down to 100 fs for GHz clock signals with a simple calibration procedure. The instrument meets the requirement of a small footprint while using a standard digital test interface to transfer data. It can be configured in different ways to suit the resolution and frequency of operation requirements. I.

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On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

Cited by 16 publications

References 20 publications

Jitter-Based Authentication for Automotive Wireline Networks

Jitter-Based Authentication for Automotive Wireline Networks

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology

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