On-Chip Millimeter Wave Antennas and Transceivers

IEEE Trans. Parallel Distrib. Syst.

Mestres

Nemirovsky

et al. 2016

Abstract-Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. For hundreds or thousands of cores, though, conventional NoCs may not suffice to fulfill the increasing on-chip communication requirements given that the performance of such networks actually drops as the number of cores grows, especially in the presence of multicast and broadcast traffic. This not only limits the scalability of current multiprocessor architectures, but also sets a performance wall that prevents the development of architectures that generate moderate-to-high levels of multicast. In this paper, a Wireless Network-on-Chip (WNoC) where all cores share a single broadband channel is presented. Such design is conceived to provide low latency and ordered delivery for multicast/broadcast traffic, in an attempt to complement a wireline NoC that will transport the rest of communication flows. To assess the feasibility of this approach, the network performance of WNoC is analyzed as a function of the system size and the channel capacity, and then compared to that of wireline NoCs with embedded multicast support. Based on this evaluation, preliminary results on the potential performance of the proposed hybrid scheme are provided, together with guidelines for the design of MAC protocols for WNoC.

Section: Phy: Towards Core-level Wireless Communicationmentioning

confidence: 88%

Scalability of Broadcast Performance in Wireless Network-on-Chip

IEEE Trans. Parallel Distrib. Syst.

Mestres

Nemirovsky

et al. 2016

“…Fed from the side, the patch radiates mostly upwards with a dipole-like behavior in the azimuth. See [12] for more details on the different antennas. For all node pairs and antenna types, we evaluate | | 2 = , / , , this is, the fraction of signal transmitted from node that is received by node .…”

Section: Discussionmentioning

confidence: 99%

Spoofing Prevention via RF Power Profiling in Wireless Network-on-Chip

Lebiednik

Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing System

Kwon

et al. 2018

With increasing integration in SoCs, the Network-on-Chip (NoC) connecting of cores and accelerators is of paramount importance to provide low-latency and high-throughput communication. Due to limits of scaling of electrical wires, especially for long multi-mm distances on-chip, alternate technologies such as Wireless NoC (WNoC) have shown promise. Since WNoCs can provide low-latency one-hop transfers across the entire chip, there has been a recent surge in research demonstrating their performance and energy benefits. However, little to no work has studied the additional security challenges that are unique to WNoCs. In this work, we study the potential threat of spoofing a ttacks i n W NoCs d ue to malicious hardware trojans. We introduce Veritas, a drop-in solution aimed at detecting and correcting such spoofing attacks. To this end, our solution exploits the static propagation environment of WNoCs to associate each node to a power profile. W e d emonstrate t hat, w ith s mall a rea and power overheads, Veritas works well in a variety of settings.

“…We will demonstrate that this is enough to provide compelling performance gains even if wireless interfaces are shared by a few computing cores. As CMOS technologies evolve and alternative technologies such as BiCMOS or graphene come into play, one can ultimately envisage integration on a per-core basis and aggregated speeds in the order of 100 Gb/s [16], [32], [33], [34].…”

Section: Overview Of Orthonocmentioning

confidence: 99%

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

IEEE Trans. Parallel Distrib. Syst.

Torrellas

Alarcón

et al. 2018

Abstract-On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents ORTHONOC, a wired-wireless architecture that differs from existing proposals in that both network planes are decoupled and driven by traffic steering policies enforced at the network interfaces. With these and other design decisions, ORTHONOC seeks to emphasize the ordered broadcast advantage offered by the wireless technology. The performance and cost of ORTHONOC are first explored using synthetic traffic, showing substantial improvements with respect to other wired-wireless designs with a similar number of antennas. Then, the applicability of ORTHONOC in the multiprocessor scenario is demonstrated through the evaluation of a simple architecture that implements fast synchronization via ordered broadcast transmissions. Simulations reveal significant execution time speedups and communication energy savings for 64-threaded benchmarks, proving that the value of ORTHONOC goes beyond simply improving the performance of the on-chip interconnect.