On-chip MOS PVT variation monitor for slew rate self-adjusting 2&amp;#x00D7;VDD output buffers

Chen, Chih-Lin; Tseng, Hsin-Yuan; Kuo, Ron-Chi; Wang, Chua-Chin

doi:10.1109/icicdt.2012.6232876

2012 IEEE International Conference on IC Design &Amp; Technology 2012

DOI: 10.1109/icicdt.2012.6232876

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On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers

Chih-Lin Chen

Hsin-Yuan Tseng

Ron-Chi Kuo

et al.

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Cited by 7 publications

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Effects of Process-Voltage-Temperature (PVT) Variations on Low-Side MOSFET circuit Conducted Emission

Baptistat¹,

Abouda²,

Duchamp³

et al. 2019

2019 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)

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On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers

Cited by 7 publications

References 6 publications

Effects of Process-Voltage-Temperature (PVT) Variations on Low-Side MOSFET circuit Conducted Emission

Effects of Process-Voltage-Temperature (PVT) Variations on Low-Side MOSFET circuit Conducted Emission

2 × VDD 28-nm CMOS digital output buffer using low-Vth transistors for slew rate adjustment

A nano-scale 2×VDD I/O buffer with encoded PV compensation technique

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