Effects of Process-Voltage-Temperature (PVT) Variations on Low-Side MOSFET circuit Conducted Emission

Baptistat, N.; Abouda, Kamel; Duchamp, Geneviève; Dubois, Tristan

doi:10.1109/emccompo.2019.8919728

Cited by 7 publications

(4 citation statements)

References 6 publications

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“…Deviations in temperature can progressively impact the performance of CMOS circuits such as oscillators. It can effect the drain current, effective mobility (µ ef f ) and the threshold voltage (V th ) of the CMOS transistors in the oscillator inverter stage [28]. The packaged PCB variant was placed in a SATIMO thermal oven with voltage biasing applied through high temperature cables (Amphenol-RF 095-902-466-004).…”

Section: B Pre-stage Study: Effect Of Temperature On the Output Frequ...mentioning

confidence: 99%

Influence of Temperature on the EFT Immunity of Multistage Integrated Oscillators

Khan

Koohestani

Perdriau

2023

IEEE Trans. Electromagn. Compat.

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The reliable operation of an integrated circuit (IC) can be affected by transient electromagnetic disturbances and temperature variations. In this paper, the performance of three oscillator circuits, namely 3-and 5-stage current-starved voltage controlled oscillators and a 3-stage ring oscillator, is compared with respect to electrical fast transients (EFT) under the influence of thermal stress. The main objective is to compare and assess, by means of measurements, the EFT immunities of integrated oscillators with the same electrostatic discharge (ESD) protections but different circuit topologies. The failure modes caused by EFT are proposed based on the considered failure criterion, i.e. the output frequency of the oscillator. Moreover, the importance of the IC package on the immunity levels of each oscillator is investigated. Additionally, the output frequency response of each oscillator to the combined EFT and temperature stresses is analyzed without the external parasitic effects. The results show that the 5-stage CSVCO is the most resilient oscillator to temperature variations, whereas it is the least immune to the combined effect of EFT and temperature. Moreover, a distinct behavior in each tested oscillator's frequency is observed for the in-phase EFT injections due to the topology of the circuit. Relevant MOSFET characteristics such as on-state drain-tosource resistance, drain currents, power dissipation, effective mobility and threshold voltage level are further analyzed under the influence of thermal stress and EFT disturbances. The root cause of higher EFT susceptibility of the 5-stage CSVCO is found to be the considerable variation of the on-state resistance due to the combined reduction of effective mobility and absolute threshold voltage levels of the MOSFETs. As a result, the power dissipation rises and causes thermal runaway.

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Section: B Pre-stage Study: Effect Of Temperature On the Output Frequ...mentioning

confidence: 99%

Influence of Temperature on the EFT Immunity of Multistage Integrated Oscillators

Khan

Koohestani

Perdriau

2023

IEEE Trans. Electromagn. Compat.

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“…Temperature variations can increasingly affect the performance of CMOS based circuits such as oscillators. It can affect the transconductance, mobility and the threshold voltage of the CMOS transistors in the oscillator inverter stage [36]. The device under test (DUT), (i.e.…”

Section: Effect Of Temperature Variation On the Integrated Oscillatorsmentioning

confidence: 99%

Experimental Characterization of Multitone EM Immunity of Integrated Oscillators Under Thermal Stress

et al. 2022

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The reliable operation of an integrated circuit can be affected by environmental changes, such as of multiple frequency electromagnetic (EM) disturbances and temperature variations. This paper compares the performance of two oscillator circuits, namely a current-starved voltage controlled oscillator and a ring oscillator integrated into a chip, in terms of their immunity to multitone direct power injection while under the influence of thermal stress. The objective is to demonstrate by the means of measurements the synergistic effect caused by multitone EM disturbances in a test chip, in contrast to the conventional single-tone EM disturbances. Moreover, the multitone immunity levels of integrated blocks with different architectures but similar functionality are analyzed at extreme temperature deviations. Bayesian networks (BN) are applied in order to visualize the probability of circuit failure due to multitone disturbances and temperature influence. Additionally, noisy-OR and improved-adaptive-recursive-noisy-OR (I-ARNOR) probabilistic models are implemented to identify the types of causal interactions (i.e. inhibition and positive causality) between multitone disturbances and to predict the probability of failure due to higher order multitone disturbances, respectively.

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“…Intermittent faults are primarily caused by the aging of electronic components and crosstalk between wires in integrated circuits. Process variations are the primary cause of transient faults [21]- [23], electromigration (EM) [24], negative bias temperature instability (NBTI) [25], hot carrier injection (HCI) [26], wear out [27], process voltage temperature variations [28], electromagnetic interference (EMI) [29], and electrostatic discharge (ESD) [30]. The intermittent faults' bursty nature causes the system to fail permanently.…”

Section: Faults and Their Effect On Interconnection Links In Nocsmentioning

confidence: 99%

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

et al. 2021

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Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, faulttolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant applicationspecific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a tablebased fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) -4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.

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Effects of Process-Voltage-Temperature (PVT) Variations on Low-Side MOSFET circuit Conducted Emission

Cited by 7 publications

References 6 publications

Influence of Temperature on the EFT Immunity of Multistage Integrated Oscillators

Influence of Temperature on the EFT Immunity of Multistage Integrated Oscillators

Experimental Characterization of Multitone EM Immunity of Integrated Oscillators Under Thermal Stress

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

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