On-Chip Networks

Abstract

Datacenter networks provide the communication substrate for large parallel computer systems that form the ecosystem for high performance computing (HPC) systems and modern Internet applications. The design of new datacenter networks is motivated by an array of applications ranging from communication intensive climatology, complex material simulations and molecular dynamics to such Internet applications as Web search, language translation, collaborative Internet applications, streaming video and voice-over-IP. For both Supercomputing and Cloud Computing the network enables distributed applications to communicate and interoperate in an orchestrated and efficient way. This book describes the design and engineering tradeoffs of datacenter networks. It describes interconnection networks from topology and network architecture to routing algorithms, and presents opportunities for taking advantage of the emerging technology trends that are influencing router microarchitecture. With the emergence of "many-core" processor chips, it is evident that we will also need "many-port" routing chips to provide a bandwidth-rich network to avoid the performance limiting effects of Amdahl's Law. We provide an overview of conventional topologies and their routing algorithms and show how technology, signaling rates and cost-effective optics are motivating new network topologies that scale up to millions of hosts.The book also provides detailed case studies of two high performance parallel computer systems and their networks.

A Survey on Reconfigurable System-on-Chips

“…Because of the limitations of bus-based architectures, bus-based SoCs cannot provide enough processing performance to keep up with this new technology trends. The Network-onChip paradigm [3] was proposed and considered as an outstanding alternative for the bus-based architecture. NoC architectures provide a higher communication performance and therefore it is a promising solution for integrating a large number of IP (Intellectual Property) cores for implementing SoCs with over one billion transistors in the future.…”

“…Such systems usually consist of several types of processing elements, such as software-programmable processors, application-specific IP cores, and especially reconfigurable processing fabrics. For connecting components of the system together, reconfigurable Network-on-chips (NoCs) [2,3] have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility in comparison with conventional on-chip bus architectures. Two key components that makes reconfigurability of a reconfigurable system are the reconfigurable processing fabrics and the reconfigurable NoC.…”

The influence of datacenter usage on symmetry in datacenter network design

“…The design of interconnection networks for distributed-memory multiprocessors and networks-on-chips is well established (see, for example, [15], which is the standard text, particularly as regards distributed-memory multiprocessors, and [40], where the focus is on networks-on-chips) and a thriving area of research. Whilst the design of DCNs is more recent, it has much in common with general interconnection network design yet there are profound differences too, prompted by, for example, usage, scale, and packaging.…”

Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

“…As router complexity increases with bandwidth demands, very simple routers (unpipelined, wormhole, no VCs, limited buffering) can be built when high throughput is not needed, so area and power overhead is low. Challenges arise when the latency and throughput demands on on-chip networks are raised [32]. A router's architecture determines its critical path delay which affects per-hop delay and overall network latency.…”