On-chip Timing Uncertainty Measurements on IBM Microprocessors

Abstract

Timing uncertainty in microprocessors is comprised of several sources including PLL jitter, clock distribution skew and jitter, across chip device variations, and power supply noise. The on-chip measurement macro called SKITTER (SKew+jITTER) was designed to measure timing uncertainty from all combined sources by measuring the number of logic stages that complete in a cycle. This measure of completed delay stages has proven to be a very sensitive monitor of power supply noise, which has emerged as a dominant component of timing uncertainty. This paper describes the Skitter measurement experiences of several IBM microprocessors including PPC970MP, XBOX360 TM , CELL Broadband Engine TM , and POWER6 TM microprocessors running different workloads.

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

“…The covariance between two parameters is determined according to the tiers to which these parameters are related and the spatial correlation between these parameters (20) where the WID covariance cov( p, q) WID is determined by the spatial correlation between parameters p and q within the same tier. Statistically, the devices (wires) close to each other have higher correlation than those far from each other.…”

“…The combination of skew and jitter, "skitter," is introduced in [20] to model the co-effect of all sources of variations on clock distribution networks, while no closedform formula is given to model the distribution of skitter. A subcircuit is designed to measure the skitter in [20], which can be utilized to mitigate undesired skitter during operation [21]. If the skitter is high, frequent recovery, and adaptation procedures have to be executed to correctly transfer data.…”

Low-Cost On-Chip Clock Jitter Measurement Scheme

“…With the scaling of technology and increase in clock frequency, it is becoming increasingly difficult to guarantee the correctness of clock signals, due to the increasing likelihood of manufacturing defects, clock jitter, duty cycle distortion, Process Parameter Variations (PPV) and Power Supply Noise (PSN) [2,3,4].…”

“…For high performance microprocessors, the adoption of minimum time margin is desirable, so that on-chip jitter measurement should be performed during the test or debug phase to validate the design and manufacturing assumptions for the clock. PSN modulating the delay of the clock signal is currently recognized as one of the main causes of clock jitter [4]. It is expected to increase with technology scaling, due to the increasing complexity and integration M. Omaña, D. Rossi, D. Giaffreda and C. Metra are with the University of Bologna, 40136, Bologna, Italy (e-mail: martin.omana@unibo.it; d.rossi@unibo.it; daniele.giaffreda2@unibo.it; cecilia.metra@unibo.it).…”

“…Several measurement schemes have been proposed for clock jitter [4][5][6][7][11][12][13][14][15] and PPV [7,16,17]. The use of ring oscillators (ROs) for PPV measurement is widely assessed and adopted.…”