On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation

Abstract

A new on-chip transient detection circuit for systemlevel electrostatic discharge (ESD) protection is proposed in this paper. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-µm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. The proposed transient detection circuit can be further cooperated with power-on reset circuit to improve the immunity of CMOS IC products against system-level ESD stress.

New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

“…It has been proven that the hardware/firmware codesign can effectively improve the robustness of microelectronic products against system-level ESD and EFT stresses [21]. To perform the hardware/firmware codesign, the detection result from the transient detection circuit can be temporarily stored as a system recover index for firmware check.…”

“…However, the additional discrete noise-bypassing components substantially increase the total cost of microelectronic products. Therefore, the chiplevel solutions to meet the high-transient-disturbance immunity specification for microelectronic products without additional discrete noise-decoupling components added on the PCB are highly desired by the IC industry [21]- [23]. In previous works, two on-chip transient detection circuits have been proposed to detect transient noise, as shown in Fig.…”

“…The modified design in Fig. 1(b) was realized with additional capacitors (C P 1 and C P 2 ) located between V DD /V SS power lines and the I/O nodes of the latch circuit to enhance its detection sensitivity [21]. However, the detection sensitivity could be degraded by the large on-chip decoupling capacitors between power lines in the CMOS IC products.…”

Electrostatic Discharge analysis of Multi Layer Ceramic capacitors

“…One effective technique is to add discrete noise-decoupling components or filters into complex CMOS based IC products to decouple, bypass, or absorb the electrical transient voltage (energy) under systemlevel ESD test [3]. Various types of noise filter networks can be employed to improve system-level ESD stress tests, including capacitor filters, ferrite bead, transient voltage suppressor (TVS), metal oxide varistor (MOV), and 2 nd order LC filter or 3 rd order -section filters.…”

Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs

“…However, most microelectronic products are required at least to automatically recover the system functions without operator intervention to meet "class B" criterion. Therefore, to meet high system-level ESD specifications for microelectronic system products, the chip-level solutions that can help the microelectronic system to execute autorecovery procedure without using additional discrete noise-decoupling components on the printed circuit board (PCB) are highly desired by the IC industry [17], [18].…”