2012 Proceedings of IEEE Southeastcon 2012
DOI: 10.1109/secon.2012.6196981
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On-chip tunable wide ranged multiple output voltage reference

Abstract: We presents an on-chip tunable wide ranged multiple output CMOS voltage reference based on non-volatile highly precise field programmable floating gate transistors. The reference is outfit for both sub 1V and above 1V applications. The circuit design consists of basic beta multiplier configuration and offers a strategy of making the current sourcing circuit and reference generating circuit as independent units. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. Simulation results show… Show more

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Cited by 1 publication
(4 citation statements)
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“…In contrast that in the proposed DVMC with M delay elements is 26M + 54K + 78 which includes 26 transistors for bias voltage generators; we used the voltage generator shown in Ref. [18]. So, it is conclude that the proposed DVMC requires 114 more transistors than the traditional DVMC.…”
Section: Area Overheadmentioning
confidence: 98%
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“…In contrast that in the proposed DVMC with M delay elements is 26M + 54K + 78 which includes 26 transistors for bias voltage generators; we used the voltage generator shown in Ref. [18]. So, it is conclude that the proposed DVMC requires 114 more transistors than the traditional DVMC.…”
Section: Area Overheadmentioning
confidence: 98%
“…[17] was used; the clock period can be set every 5.2 ps from 500 ps to 1,000 ps. We used an on-chip tunable wide ranged multiple output voltage reference circuit [18] to generate the bias voltage of V biasp and V biasn for the DTC inverter; the generator of Ref. [18] can generate bias voltages with 13-bit resolution [19].…”
Section: Resolutionmentioning
confidence: 99%
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