A Calibration Technique for DVMC with Delay Time Controllable Inverter

Cui, Ri; Namba, Kazuteru

doi:10.2197/ipsjtsldm.9.30

Cited by 3 publications

(4 citation statements)

References 18 publications

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“…Calibration method described in Ref. [14] adds a delay time controllable (DTC) inverter to TDC. By gradually increasing or decreasing the delay of DTC inverter and deciding the point where measured delay value increases or decreases, calibration accuracy improves.…”

Section: Comparison With Tdcmentioning

confidence: 99%

“…By gradually increasing or decreasing the delay of DTC inverter and deciding the point where measured delay value increases or decreases, calibration accuracy improves. Reference [14] achieves 0.58 ps calibration accuracy with 5.2 ps resolution clock source.…”

Section: Comparison With Tdcmentioning

confidence: 99%

“…Time-to-digital converters (TDC) has the potential to measure circuit delay with high accuracy [14], and is used to measure the delay of critical path replica in Ref. [5].…”

Section: Introductionmentioning

confidence: 99%

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Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator

Shimamura

Ikeda

2020

IPSJ Transactions on System LSI Design Methodology

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With the progress of semiconductor process miniaturization, delay degradation by aging increases and threatens the reliability of fabricated chips. The amount of delay degradation is known to be circuit and workload dependent, but previous evaluations are based on simulations, and delay degradation measurement of real circuit under realistic workload has not been reported yet. This paper proposes real circuit delay measurement method, which achieves enough accuracy to measure circuit and workload dependent delay degradation. In the proposed method, onchip oscillator supplies fine resolution variable frequency clock to internal circuit. Internal circuit execute test pattern to activate critical paths at various frequency and determine the maximum frequency at which correct results can be obtained. The maximum frequency corresponds to the delay of the critical paths activated by the test pattern. Clock multiplication improves delay resolution, and repetitive measurement reduces measurement error caused by time dependent random delay variation. The proposed method has been implemented on a 65 nm low power process test chip. Variable frequency oscillator utilizes only standard cells and is designed with automatic layout flow without any timing tuning. The area overhead of the proposed method is 0.09% of the total random logic. The evaluation result show that 0.18% average measurement accuracy has been achieved.

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Section: Comparison With Tdcmentioning

confidence: 99%

Section: Comparison With Tdcmentioning

confidence: 99%

See 1 more Smart Citation

Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator

Shimamura

Ikeda

2020

IPSJ Transactions on System LSI Design Methodology

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show abstract

“…In the case of a TDC, the goal is to obtain a linear relation between the timing between an edge of an input digital signal and a reference clock edge. Many calibration methods have been proposed, such as statistical code density testing [3], wave-union [9], direct-to-histogram [10], multi-phase sampling [11], variable clock generation [12]- [14], and dynamic reconfiguration [15], [16].…”

Section: Introductionmentioning

confidence: 99%

High-Resolution Waveform Capture Device on a Cyclone-V FPGA

2021

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We introduce the waveform capture device (WCD), a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD is implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA, Intel/Altera Cyclone V), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It is calibrated via a novel dynamic phase-shifting (DPS) method that requires substantially less data and resources than the state-of-the-art. Using DPS, we find the measurement resolution -or mean propagation delay from one CC element to the next -to be 4.91±0.04 ps (4.54±0.02 ps) for a pulse of logic high (low). Similarly, we find the single-shot precision -or mean error on the timing of the waveform -to be 29.52 ps (27.14 ps) for pulses of logic high (low). We verify these findings by reproducing commercial oscilloscope measurements of asynchronous ring-oscillators on FPGAs, finding the mean pulse width to be 0.240 ± 0.002 ns per inverter gate. Finally, we present a careful analysis of design constraints, introduce a novel error correction algorithm, and sketch a simple extension to the analog domain. We also provide the Verilog code instantiating our design's hardware primitives in an Appendix, and make our FPGA interfacing methods available as an open-source Python library at https://github.com/Noeloikeau/fpyga.

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High-Resolution Waveform Capture Device on a Cyclone-V FPGA

Charlot¹,

Gauthier²,

Pomerance³

2021

Preprint

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We introduce the waveform capture device (WCD), a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD is implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA, Intel/Altera Cyclone V), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It is calibrated via a novel dynamic phase-shifting (DPS) method that requires substantially less data and resources than the state-of-the-art. Using DPS, we find the measurement resolution -or mean propagation delay from one CC element to the next -to be 4.91 ± 0.04 ps (4.54 ± 0.02 ps) for a pulse of logic high (low). Similarly, we find the single-shot precision -or mean error on the timing of the waveform -to be 29.52 ps (27.14 ps) for pulses of logic high (low). We verify these findings by reproducing commercial oscilloscope measurements of asynchronous ring-oscillators on FPGAs, finding the mean pulse width to be 0.240 ± 0.002 ns per inverter gate. Finally, we present a careful analysis of design constraints, introduce a novel error correction algorithm, and sketch a simple extension to the analog domain. We also provide the Verilog code instantiating the our design on an FPGA in an Appendix, and make our methods available as an open-source Python library at https://github.com/Noeloikeau/fpyga. INDEX TERMSTime-to-Digital Converter (TDC), Digital Storage Oscilloscope (DSO), Field Programmable Gate Array (FPGA), Phase Lock Loop (PLL), Dynamic Phase Shift (DPS), Carry Chain (CC)

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A Calibration Technique for DVMC with Delay Time Controllable Inverter

Cited by 3 publications

References 18 publications

Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator

Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator

High-Resolution Waveform Capture Device on a Cyclone-V FPGA

High-Resolution Waveform Capture Device on a Cyclone-V FPGA

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