On computing multiplicative inverses in GF(2/sup m/)

Brunner, Hermann; Curiger, Andreas; Hofstetter, M.

doi:10.1109/12.238496

Cited by 123 publications

(61 citation statements)

References 8 publications

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“…The extended Euclid's algorithm usually requires the field element having a polynomial basis representation [5], where the most used operations are field addition, shifting and loading. Efficient algorithms have been proposed for the second method, for example, [8] and [2].…”

Section: Inversionmentioning

confidence: 99%

Low Complexity Bit-Parallel Finite Field Arithmetic Using Polynomial Basis

Wu¹

1999

Cryptographic Hardware and Embedded Systems

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Abstract. Bit-parallel finite field multiplication in F2m using polynomial basis can be realized in two steps: polynomial multiplication and reduction modulo the irreducible polynomial. In this article, we prove that the modular polynomial reduction can be done with (r − 1)(m − 1) bit additions, where r is the Hamming weight of the irreducible polynomial. We also show that a bit-parallel squaring operation using polynomial basis costs not more than m + k − 1 2 bit operations if an irreducible trinomial of form x m + x k + 1 over F2 is used. Consequently, it is argued that to solve multiplicative inverse in F2m using polynomial basis can be as good as using normal basis.

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Section: Inversionmentioning

confidence: 99%

Low Complexity Bit-Parallel Finite Field Arithmetic Using Polynomial Basis

Wu¹

1999

Cryptographic Hardware and Embedded Systems

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“…Several algorithms have been introduced for computing field inversion/division operation based on the Extended Euclidean algorithm [2][3][4][5][6]. Although these algorithms can be easily implemented using software programs on a general-purpose computer, they would be slow and inefficient for public key cryptosystems which is used a very large field [3,4].…”

Section: Ecc (Elliptic Curvementioning

confidence: 99%

Design of Iterative Divider in GF(2163

Kang¹,

Jeon²

2010

The KIPS Transactions:PartC

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In this paper, we first propose a fast division algorithm in GF(2 163 ) using standard basis representation, and then it is mapped into divider for GF(2 163 ) with iterative hardware structure. The proposed algorithm is based on the binary ExtendedGCD algorithm, and the arithmetic operations for modular reduction are performed within only one "while-statement" unlike conventional approach which uses two "while-statement". In this paper, we use reduction polynomial f(x)=x 163 +x 7 +x 6 +x 3 +1 that is recommended in SEC2(Standards for Efficient Cryptography) using standard basis representation, where degree m = 163. We also have implemented the proposed iterative architecture in FPGA using Verilog HDL, and it operates at a clock frequency of 85 MHz on Xilinx-VirtexII XC2V8000 FPGA device. From implementation results, we will show that computation speed of the proposed scheme is significantly improved than the existing two approaches.

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“…BMA is based on a t-step recursive procedure, which cannot be parallelized completely. Each iteration involves a Galois field inversion that takes 2m steps [4]. An inversionless BMA proposed in [6] uses double the number of multiplications, but performs them in parallel and off the critical path [21].…”

Section: Ecc Overhead Analysismentioning

confidence: 99%

Energy-efficient cache design using variable-strength error-correcting codes

Alameldeen

Wagner

Chishti

et al. 2011

Proceedings of the 38th Annual International Symposium on Computer Architecture

110

101

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Voltage scaling is one of the most effective mechanisms to improve microprocessors" energy efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin, since hardware structures may fail. Cell failures in large memory arrays (e.g., caches) typically determine Vccmin for the whole processor. We observe that most cache lines exhibit zero or one failures at low voltages. However, a few lines, especially in large caches, exhibit multi-bit failures and increase Vccmin. Previous solutions either significantly reduce cache capacity to enable uniform error correction across all lines, or significantly increase latency and bandwidth overheads when amortizing the cost of error-correcting codes (ECC) over large lines.In this paper, we propose a novel cache architecture that uses variable-strength error-correcting codes (VS-ECC). In the common case, lines with zero or one failures use a simple and fast ECC. A small number of lines with multi-bit failures use a strong multi-bit ECC that requires some additional area and latency. We present a novel dynamic cache characterization mechanism to determine which lines will exhibit multi-bit failures. In particular, we use multi-bit correction to protect a fraction of the cache after switching to low voltage, while dynamically testing the remaining lines for multi-bit failures. Compared to prior multi-bit-correcting proposals, VS-ECC significantly reduces power and energy, avoids significant reductions in cache capacity, incurs little area overhead, and avoids large increases in latency and bandwidth.

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On computing multiplicative inverses in GF(2/sup m/)

Cited by 123 publications

References 8 publications

Low Complexity Bit-Parallel Finite Field Arithmetic Using Polynomial Basis

Low Complexity Bit-Parallel Finite Field Arithmetic Using Polynomial Basis

Design of Iterative Divider in GF(2163

Energy-efficient cache design using variable-strength error-correcting codes

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