On Delay Test Generation for Non-scan Sequential Circuits at Functional Level

Abstract

Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection. High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. We investigated the application of tests that are generated at functional level for detection of gate-level transition faults. Based on experimental results, we developed a framework of delay test generation for non-scan sequential circuits. The provided comparison with experimental results of other approaches demonstrates the effectiveness of proposed framework. Bibl. 13, tabl. 4 (in English; abstracts in English and Lithuanian).http://dx.doi.org/10.5755/j01.eee.109.3.173

Verification of Initialization Sequences for Sequential Circuits

“…Verification normally approves the found solution, yet sometimes the solution does not pass through [11]. In this case, the validation process outputs the number of fixed flip-flops.…”

“…Both methods have their advantages and disadvantages. [1][2][3][4][5][6][7][8][9][10][11][12] An initializing sequence may not exist, be too long, or set a circuit into an undesired state [1][2][3][4]. Using scan allows easy flip-flop setting, but also increases chip size due to direct access requirement.…”

An Investigation of Possibilities of Improving Random Test Generation for Non-scan Sequential Circuits

“…The delay fault test for non-scan synchronous sequential circuits could be constructed at the functional level using the software prototype model, as well [3,4,7].…”

“…Random test sequences may be used for manufacturing testing as well as for simulation-based design verification [1][2][3][4]. The presented in [3,4] research shows that functional tests designed using random test generation exhibit better transition fault coverages than tests produced by deterministic ATPG tools.…”

“…Random test sequences may be used for manufacturing testing as well as for simulation-based design verification [1][2][3][4]. The presented in [3,4] research shows that functional tests designed using random test generation exhibit better transition fault coverages than tests produced by deterministic ATPG tools. Therefore, we are going to investigate further the possibilities of improving random test generation for at-speed testing of non-scan synchronous sequential circuits in this paper.…”