On Design of Parity Preserving Reversible Adder Circuits

Haghparast, Majid; Bolhassani, Ali

doi:10.1007/s10773-016-3133-5

Cited by 6 publications

(6 citation statements)

References 38 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…14 To date, several PP reversible gates have been introduced. For the realization of the proposed design, five most essential gates 14,[31][32][33][34] have been used. The characteristics of these gates and also their size and quantum cost are presented in Figure 4.…”

Section: Existing Parity Preserving Reversible Gatesmentioning

confidence: 99%

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

Noorallahzadeh

Mosleh

Ahmadpour

et al. 2023

Int J Numerical Modelling

View full text Add to dashboard Cite

Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.

show abstract

Section: Existing Parity Preserving Reversible Gatesmentioning

confidence: 99%

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

Noorallahzadeh

Mosleh

Ahmadpour

et al. 2023

Int J Numerical Modelling

View full text Add to dashboard Cite

show abstract

“…In order to detect bit errors of reversible-circuits, we can design them with PP ability [30][31][32][33][34]. In the following section, we introduce three PPR logic blocks, including Double Feynman Gate (DFG), FRedkin-Gate (FRG), and Bolhassani Haghparast Parity-Preserving Full-adder (BHPF) gates.…”

Section: Reversible Gatesmentioning

confidence: 99%

Effective scheme of parity-preserving-reversible floating-point divider

et al. 2022

Self Cite

View full text Add to dashboard Cite

Most recently, there has been a growing need for developing very large-scale integration (VLSI) circuits with low energy consumption and high speed for use in fast transmission systems. In addition, the main challenge in designing irreversible integrated circuits is heat generation due to data loss. Thus, in recent years, reversible design has been preferred for low-power VLSI circuits because the data is not lost. In this article, a new design of parity-preserving-reversible (PPR) floating-point divider is suggested. A floating-point divider structure includes parallel adder, multiplexer, register, and left-shift register. To optimize these circuits, first, we propose a 5×5 PPR block and a PPR D-latch. Second, using the proposed circuits, a ripple-carry-adder (RCA), a register, and an efficient parallel-input-parallel-output (PIPO)-left-shift register, rounding-register, and normalization register circuits are introduced in PPR logic. The comparisons illustrate that the suggested circuits are preferable to the circuits presented in previous works in terms of various criteria such as quantum cost, constant inputs, and garbage outputs.

show abstract

“…There are so many reversible adder and multiplier implementation methods [M. Haghparast et. al 2016].…”

Section: Universal Computational Circuit (Adder Cum Subtractor)mentioning

confidence: 99%

Performance Analysis of a Universal Circuit for Reversible ALU using QCA & CMOS Technology

Tiwari¹,

Kumar²,

Shara³

2018

IJET

View full text Add to dashboard Cite

The reversible logic and gates are one of the promising and upcoming technologies which are capable of overcoming the limitations of the design and applications based on the CMOS technology. In this technology, the schematic arrangement of the device is implemented in such a way that every input terminal has been provided with individual output terminals. The author has used the technology which is based on quantum computations with a basic feature of loss of energy in small amount. It has many advantages like very high operating speed, low energy dissipation, and high device density. An adder/subtractor is heart of arithmetic units of processors i.e. acts as universal circuit for carrying out the mathematical computations in the quantum processors. The author has put forward a novel reversible adder/subtractor circuit using reversible logic & QCA. The QCA based circuit reported by the author has been compared and analyzed for the performance on the basis of number of gates, size, delay, power dissipation etc. The experimental work has been completed with the use of the most suitable and reliable software i.e. QCA and the performance of the proposed circuit has proven to be quite useful for this circuit to be used in some promising applications. These results are also compared with those obtained with the use of CMOS Technologies.

show abstract

On Design of Parity Preserving Reversible Adder Circuits

Cited by 6 publications

References 38 publications

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

Effective scheme of parity-preserving-reversible floating-point divider

Performance Analysis of a Universal Circuit for Reversible ALU using QCA & CMOS Technology

Contact Info

Product

Resources

About