This paper compares the power efficiency of multiple 2D, 2.5D and 3D interconnect scenarios, specifically DDR3 with PCB, DDR3 with interposers, LPDDR2(3) with POP, wide I/Os with through-silicon vias (TSVs) and interposers and 32 nm technology CMOS drivers with TSVs and on-chip wires. It was found that DDR3 with PCB is the lowest power efficiency (15.65 mW/Gbps) and custom designed CMOS drivers optimized for the 2.5D and 3D give the highest power efficiency (0.23mW/Gbps). Optimization of a Back End of the Line (BEOL) 65 nm interposer interface is also presented for Wide IO interface to find maximize power efficiency. Power efficiency for different interposer trace lengths (5mm-40mm) and pitches (4.6µm-11.05µm) was analyzed. It was found that power efficiency decreases linearly with the increase of pitch and length of the interposer traces both in one stack and 4 stack die of Wide IO.

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The reversible logic and gates are one of the promising and upcoming technologies which are capable of overcoming the limitations of the design and applications based on the CMOS technology. In this technology, the schematic arrangement of the device is implemented in such a way that every input terminal has been provided with individual output terminals. The author has used the technology which is based on quantum computations with a basic feature of loss of energy in small amount. It has many advantages like very high operating speed, low energy dissipation, and high device density. An adder/subtractor is heart of arithmetic units of processors i.e. acts as universal circuit for carrying out the mathematical computations in the quantum processors. The author has put forward a novel reversible adder/subtractor circuit using reversible logic & QCA. The QCA based circuit reported by the author has been compared and analyzed for the performance on the basis of number of gates, size, delay, power dissipation etc. The experimental work has been completed with the use of the most suitable and reliable software i.e. QCA and the performance of the proposed circuit has proven to be quite useful for this circuit to be used in some promising applications. These results are also compared with those obtained with the use of CMOS Technologies.

Background: In WDM networks, there is a crucial need to monitor signal degradation factors in order to maintain the quality of transmission. This is more critical in dynamic optical networks as non-linear impairments are network state dependent. Moreover, PLIs are accumulative in nature, so the overall impact is increased tremendously as the length of signal path is increased. The interactions between different impairments along the path also influence their overall impact. Objective: Among the different impairments, the present work focus on phase modulations owing to intensities of signals themselves as well as the neighboring signals. It includes the influence of SPM, SPM and XPM, system parameters like signal power, wavelength and fiber parameters like attenuation coefficient, dispersion coefficient and their influence on Q-value and BER. Method: The analysis is done through a single and two-channel transmitter system with varied power, wavelengths and system parameters. The corresponding optical spectrums are analysed. Result & Conclusion: It has been found that SPM and XPM pose broadening effect on spectrum without any effect on temporal distributions. The magnitude of signal power is among the parameters significantly influencing the broadening of spectrum. Higher is the power, more is the magnitude of broadening. It has been found that in order to neglect the impact of input power; its magnitude must be kept below 20 mW. Also, the dispersion and attenuation value need to be carefully as they pose counteracting effect to SPM and XPM for certain values and hence can be used as compensation measure without any additional cost.