Power comparison of 2D, 3D and 2.5D interconnect solutions and power optimization of interposer interconnects

Karim, M. A.; Franzon, Paul D.; Kumar, Anil

doi:10.1109/ectc.2013.6575674

Cited by 32 publications

(23 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The data presented in Figure 3 (taken from [2]) compares the power efficiency of a subset of these, and other, interface standards. This data highlights the significant power efficiency advantage of 3D technologies over conventionally packaged solutions.…”

Section: B Memory Bandwidth and Powermentioning

confidence: 99%

Applications and design styles for 3DIC

Franzon

Rotenberg

Tuck

et al. 2013

2013 IEEE International Electron Devices Meeting

Self Cite

View full text Add to dashboard Cite

3D technologies offer significant potential to improve raw performance and performance per unit power.After exploiting TSV technologies for cost reduction and increasing memory bandwidth, the next frontier is to create more sophisticated solutions that promise further increases in power/performance beyond those attributable to memory interfaces alone. These include heterogeneous integration and exploitation of the high amounts of interconnect available to provide for customization. Challenges include the creation of physical standards and the design of sophisticated static and dynamic thermal management methods.

show abstract

Section: B Memory Bandwidth and Powermentioning

confidence: 99%

Applications and design styles for 3DIC

Franzon

Rotenberg

Tuck

et al. 2013

2013 IEEE International Electron Devices Meeting

Self Cite

View full text Add to dashboard Cite

show abstract

“…We demonstrate our methodology by integrating Wide I/O memory [11] and multi-partition logics on a 2.5D/3D package interfaced with a monolithic SOC flip chip die realized on a multi-layer organic build-up substrate. The flip chip SOC package is subsequently interfaced with a rigid silicon interposer package, a DDR4 package, a connector and a wirdebonded BGA laminate package on the PCB (Fig.…”

Section: Introductionmentioning

confidence: 99%

Pathfinding methodology for optimal design and integration of 2.5D/3D interconnects

Yazdani¹,

Park

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

Given the cost per transistor is to grow below 22nm node, SOC partitioning is emerging as a viable solution compared to a monolithic solution. Ubiquitous 2.5D/3D heterogeneous integration is evolving as an eminent approach to achieve lower cost, higher bandwidth, smaller footprint and lower power. System partitioning schemes and heterogeneous integration mechanisms directly impacts performance, cost and time to market. Partitioning a single die into multiple partitions for further heterogeneous integration requires an ultra-dense connectivity.One of the key challenges in designing a low cost and high performance 2.5D/3D package is the system-level ultra-dense connectivity exploration and pathfinding. Planning an I/O ring structure and defining I/O buffer cell placement for multiple logic partitions at the early stages of 2.5D/3D product development is not trivial. Moreover, endto-end optimization of inter-partition's I/O cell placement, Cu pillar bump matrix and package BGA interfaced with numerous components on the PCB with fixed ball patterns is a daunting task.In this communication, we present a pathfinding methodology for the design and optimization of 2.5D/3D interconnects. We demonstrate our methodology in a 2.5D/3D design where inter-partition's I/O buffer cells placement, Cu pillar bump matrix and package BGA are optimized in a hierarchical fashion with respect to the Wide I/O memory's fixed bump pattern interfaced with the PCB level components placement and connectivity. We further demonstrate the cross domain flexibility and robustness of our methodology by performing an end-to-end pathfinding on ultra-dense 2.5D/3D silicon interposer and single SOC device interfaced with fixed components on a PCB.

show abstract

“…A recent work has shown that interconnects on a silicon interposer have high power efficiency for smaller pitch due to small ground capacitance [4]. However, other important design objectives have not been investigated in [4].…”

Section: Introductionmentioning

confidence: 99%

“…However, other important design objectives have not been investigated in [4]. In addition, other materials, such as glass with potential performance benefits need to be explored [2].…”

Section: Introductionmentioning

confidence: 99%

Interconnect design tradeoffs for silicon and glass interposers

Kalargaris

Pavlidis

2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

View full text Add to dashboard Cite

Interposer technologies offer high density, high performance interconnects for integrated systems resulting in smaller form factors and improved system performance as compared to traditional packages. This paper sheds light on the different design tradeoffs which result from the usage of silicon and glass interposers due to the different material characteristics. The emphasis is on the redistribution layers (RDLs) of the interposer rather than the through silicon vias (TSVs) due to the long length of these wires. Guidelines of designing the interconnects for different design objectives on silicon and glass interposers are presented. Interconnects on glass interposers are more efficient in terms of power dissipation and delay. Conversely, wires on glass interposers suffer from twice as high crosstalk as compared to silicon at minimum pitch. Interconnects on glass interposers exhibit 35% better power-delay product (PDP) than on silicon for fixed pitch at 1.95 µm. More importantly, minimum pitch does not result in minimum delay, power dissipation, and crosstalk. The interconnect design parameters that satisfy these objectives under different constraints are different for the two materials. Consequently, the various tradeoffs between area and noise as well as power and delay must be considered in the design process.

show abstract

Power comparison of 2D, 3D and 2.5D interconnect solutions and power optimization of interposer interconnects

Cited by 32 publications

References 3 publications

Applications and design styles for 3DIC

Applications and design styles for 3DIC

Pathfinding methodology for optimal design and integration of 2.5D/3D interconnects

Interconnect design tradeoffs for silicon and glass interposers

Contact Info

Product

Resources

About