On detecting delay anomalies introduced by hardware trojans

Ismari, Dylan; Plusquellic, Jim; Lamech, Charles; Bhunia, Swarup; Saqib, Fareena

doi:10.1145/2966986.2967061

Cited by 23 publications

(6 citation statements)

References 12 publications

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“…Ismari et al [40] Delay based SCA Simulation On-chip embedded test structure to reduce effects of intra-die PV Esirci et al [27] Delay based SCA Simulation Statistical analysis of delays in correlated paths 2017 He et al [35] EM based SCA Simulation Simulation data from RTL design is used to generate the EM fingerprint 2017 Sree et al [65,67] ATPG with SCA Self-Referencing…”

Section: Discussionmentioning

confidence: 99%

“…The resultant path delay ratio(ratio of suspected path to correlated path) values of the HT infected IC must be a significantly larger from the ratio values of the HT-free IC. A delay-based detection method has been proposed in [40] which uses a high resolution on-chip embedded test structure called a time-to-digital converter (TDC) that provides timing resolution of approximately 25 ps. A novel chip-averaging technique is also devised which reduce the adverse effects of intra-die process variations on HT detection.…”

Section: Path Delay Characterization Basedmentioning

confidence: 99%

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SoK

Rajendran

Mukherjee

Chakraborty

2020

Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security

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Hardware Trojans have emerged as great threat to the trustability of modern electronic systems. A deployed electronic system with one or more undetected Hardware Trojan-infected components can cause grave harm, ranging from personal information loss to destruction of national infrastructure. The inherently surreptitious nature and bewildering variety of Hardware Trojans makes their detection an extremely challenging exercise. In this paper, we explore the state-of-the-art of non-destructive testing for Hardware Trojan detection, with our coverage including both physical measurement based testing, as well as logic testing. We present systematic classification of Hardware Trojans and their detection techniques, and describe these techniques in details, including their stand-out features and strengths and weaknesses. We conclude the paper with an evaluation of the current status of progress, and major directions of future research. CCS CONCEPTS • Hardware → Design for testability; On-chip sensors; • Security and privacy → Hardware reverse engineering; Hardware attacks and countermeasures.

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Section: Discussionmentioning

confidence: 99%

Section: Path Delay Characterization Basedmentioning

confidence: 99%

SoK

Rajendran

Mukherjee

Chakraborty

2020

Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security

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“…The efficiency of the method decreases with the increasing number of high fanout nets in the design. A high resolution on-chip embedded test structure called timeto-digital converter (TDC) for measuring path delays and a chip-averaging technique was proposed to detect delay anomalies introduced by HTs in [19]. An on-chip self-referencing based HT detection method was proposed in [16].…”

Section: Related Workmentioning

confidence: 99%

Variability aware Golden Reference Free methodology for Hardware Trojan Detection Using Robust Delay Analysis

Ramakrishna¹,

Sahula²,

Bhargava³

2022

Preprint

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Many fabless semiconductor companies outsource their designs to third-party fabrication houses. As trustworthiness of chain after outsourcing including fabrication houses is not established, any adversary in between, with malicious intent may tamper the design by inserting Hardware Trojans (HTs). Detection of such HTs is of utmost importance to assure the trust and integrity of the chips. However, the efficiency of detection techniques based on side-channel analysis is largely affected by process variations. In this paper, a methodology for detecting HTs by analyzing the delays of topologically symmetric paths is proposed. The proposed technique, rather than depending on golden ICs as a reference for HT detection, employs the concept of self-referencing. In this work, the fact that delays of topologically symmetric paths in an IC will be affected similarly by process variations is exploited. A procedure to chose topologically symmetric paths that are minimally affected by process variations is presented. Further, a technique is proposed to create topologically symmetric paths by inserting extra logic gates if such paths do not exist in the design intrinsically. Simulations performed on ISCAS-85 benchmarks establish that the proposed method is able to achieve a true pos-

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“…Conventional manufacturing VLSI test and verification methodologies fall short in detecting HW Trojans due to the different and un-modeled nature of these malicious alterations. This has led many researchers to investigate solutions for detection of HW Trojans through statistical analysis of side-channel information collected from ICs, including sidechannel power analysis [1]- [6], power supply transient signal analysis [7], [8], regional supply currents analysis [9], temperature analysis [10], wireless transmission power analysis [11], and side-channel delay analysis [12]- [18].…”

Section: Introductionmentioning

confidence: 99%

LASCA: Learning Assisted Side Channel Delay Analysis for Hardware Trojan Detection

Vakil¹,

Behnia²,

Mirzaeian³

et al. 2020

Preprint

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In this paper, we introduce a Learning Assisted Side Channel delay Analysis (LASCA) methodology for Hardware Trojan detection. Our proposed solution, unlike the prior art, does not require a Golden IC. Instead, it trains a Neural Network to act as a process tracking watchdog for correlating the static timing data (produced at design time) to the delay information obtained from clock frequency sweeping (at test time) for the purpose of Trojan detection. Using the LASCA flow, we detect close to 90% of Hardware Trojans in the simulated scenarios.

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On detecting delay anomalies introduced by hardware trojans

Cited by 23 publications

References 12 publications

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Variability aware Golden Reference Free methodology for Hardware Trojan Detection Using Robust Delay Analysis

LASCA: Learning Assisted Side Channel Delay Analysis for Hardware Trojan Detection

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