On-die learning-based self-calibration of analog/RF ICs

Volanis, Georgios; Maliuk, Dzmitry; Lu, Yao; Subramani, Kiruba Sankaran; Antonopoulos, Angelos; Makris, Yiorgos

doi:10.1109/vts.2016.7477297

Cited by 11 publications

(11 citation statements)

References 12 publications

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“…Most self-healing methodologies developed in the literature are largely focused on process variations, that are becoming a show-stopper in the design of analog and RF circuits [1], [2]. Numerous self-calibration techniques have been presented, that can be classified in two categories [3], depending if they are based on direct performance measurements [3]- [5], or if they rely on statistical techniques [1], [2], [6]- [8]. Direct methodologies aim to evaluate performance targets directly while integrating a maximum of the measurement and analysis circuitry on-chip to reduce test cost.…”

Section: B Sota On Analog/rf Self-calibrationmentioning

confidence: 99%

“…However, a lot of tests are necessary and the procedure is difficult to extend for other circuits. As an example of a statistical methodology, [6] implements a on-chip neural network in the analog domain. This enables, after training, to predict a figure of merit (FoM) for a low-noise amplifier, representative of a trade-off between its main performances.…”

Section: B Sota On Analog/rf Self-calibrationmentioning

confidence: 99%

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From on-chip self-healing to self-adaptivity in analog/RF ICs: challenges and opportunities

Andraud

Verhelst

2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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The numerous variations that affect analog and RF circuits are becoming a limiting factor in the design of these circuits in deeply scaled CMOS technologies. An emerging idea to counteract these effects is to let the circuit compensate for these variations itself, referred to as self-healing. Over the last decade, a wide variety of off-and on-chip techniques for compensating these variations have been researched. This paper targets to give an overview of the state-of-the-art, and organize the proposed techniques in a common taxonomy. This allows to determine remaining open issues and research challenges. In particular, the SotA lacks efficient solutions for fully-integrated, short time-scale self-adaptation. The paper ends by giving an outlook towards promising research directions to enable such self-adaptation in mWatt power budgets for Internet of things applications, focusing on embedded machine-learning techniques.

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Section: B Sota On Analog/rf Self-calibrationmentioning

confidence: 99%

Section: B Sota On Analog/rf Self-calibrationmentioning

confidence: 99%

From on-chip self-healing to self-adaptivity in analog/RF ICs: challenges and opportunities

Andraud

Verhelst

2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…Then, at postmanufacturing time, calibration is achieved by: (a) measuring the process sensor values with the BIST structures, (b) predicting the circuit performances through the machine-learning model and (c) determining the best tuning knob settings to achieve the desired performance. This stage can take place off-chip [5], [6] or on-chip [4], [7], [8] as illustrated in fig. 1.…”

Section: B Statistical Self-calibration Techniquesmentioning

confidence: 99%

“…However, this technique assumes that each knob control a specific performance parameter independently of the other, which is a desirable attribute but often difficult to achieve in practice during design. In [8] it is proposed to avoid crossing the digital domain and efficiently implement a NN directly in the analog domain. The best tuning knob settings are subsequently found by measuring the process sensors exhaustively going through the tuning knob combinations to find the best one.…”

Section: B Statistical Self-calibration Techniquesmentioning

confidence: 99%

“…Self-calibration using only a single test iteration, called "oneshot", have even recently been presented [5]- [7]. One step further is to fully integrate the calibration procedure on-chip, following up on Built-In Self-Test (BIST) developments [8], [9]. Several benefits can be expected, such as a further reduction of post-manufacturing calibration cost and time.…”

Section: Introductionmentioning

confidence: 99%

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On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs

Andraud

Galindez

et al. 2018

2018 IEEE International Test Conference (ITC)

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Over the past few years, several self-calibration methodologies have proven their efficiency to calibrate analog and radio-frequency circuits against process variations. Specifically, statistical techniques based on machine-learning have been proposed to recover yield loss and even enhance circuit performances. In addition, these techniques enable to calibrate circuits after a single performance test, i.e. in one-shot. However, towards fully-integrated calibration techniques, the inference part of the machine learning algorithm needs to be performed as energyefficiently as possible to reduce calibration cost to a minimum. Following the path of resource-efficient machine learning, this work explores an alternative to state-of-the-art Neural Network based statistical techniques. Specifically, we investigate the opportunities of using Bayesian Networks for resource-efficient onchip statistical calibration of analog/RF circuits. Results will show that several improvements can be achieved using Bayesian Networks: (a) provide a comprehensive calibration framework with explicit relationships between parameters (b) demonstrate similar prediction accuracies that neural networks (c) optimize across several performance parameters with a single network and in a single query and (d) enable a more energy-efficient hardware implementation. The proposed self-calibration algorithm is applied to a low-noise amplifier fabricated with IBM's 130nm CMOS process, leading to a significant reduction in the number of operations required to obtain the best tuning knob setting.(1) With off-chip post-manufacturing phase (2) With a fully on-chip procedure Off-line training phase On-line (and/or on-chip) phase Optimal Tuning Knobs BUILT-IN TEST

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