On Effective Through-Silicon Via Repair for 3-D-Stacked ICs

Abstract

3-D-stacked integrated circuits (ICs) that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3-Dstacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleanness of silicon dies, rendering prior TSV redundancy solutions less effective. Furthermore, existing techniques consume a lot of redundant TSVs that are still costly in the current TSV process. This inefficient TSV redundancy can limit the amount of TSVs that is allowed to use and may even become the obstacle to commercial production. To resolve this problem, we present a novel TSV repair framework, including a hardware redundancy architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, the corresponding repair algorithm and the redundancy architecture construction. By doing so, the manufacturing yield for 3-Dstacked ICs can be dramatically improved, as demonstrated in our experimental results. Index Terms-3-D stacking, redundancy, through-silicon vias (TSV) repair, yield enhancement.

An Effective TSV Self-Repair Scheme for 3D-Stacked ICs

“…The functional verification for the proposed TSV repair scheme is conducted by using HSPICE. In the second experiment, the average of TSV defective probability is assumed between 5×10 -5 and 1×10 -3 , which is a reasonable range as reported in [15].…”

“…Jiang et al [15] proposed a TSV redundancy architecture using dedicated switches to handle clustered TSV faults. Based on this architecture, the corresponding repair algorithm is also presented.…”

“…This scheme is built upon the TSV repair architecture previously proposed in [15], assuming there exists a processor and a nonvolatile memory in the 3D-stacked IC. In the proposed scheme, the online testing is conducted periodically or triggered by events firstly.…”

“…For simplicity, an average defective probability, denoted as p, can be assumed for calculating the R x . Then (2) can be approximated as [15]  …”

Fault diagnosis of TSV-based interconnects in 3-D stacked designs

“…Because of such imperfect etching, ragged wafer surface, and potential wafer misalignments, certain TSVs in one wafer after thinning and polishing might not be completely exposed or aligned with their counterparts on the other wafer [14], [23]. Since the bonding quality of TSVs depends on the winding level of the thinned wafer as well as the surface roughness and cleanness of silicon dies, defective TSVs tend to occur in clusters [10], though even a single TSV defect between any two layers can void the entire chip stack, reducing the overall yield.…”