On energy efficiency of reconfigurable systems with run-time partial reconfiguration

Liu, Shaoshan; Pittman, Richard Neil; Form, Alessandro; Gaudiot, Jean‐Luc

doi:10.1109/asap.2010.5540985

Cited by 18 publications

(8 citation statements)

References 9 publications

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“…(c) PR has also been used to save power by blanking unused PRRs with blank bitstreams. For PR blanking of a region to provide an energy saving, it is required that [6]:…”

Section: Partial Reconfigurationmentioning

confidence: 99%

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq

Vipin

Fahmy

2014

IEEE Embedded Syst. Lett.

104

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“…(c) PR has also been used to save power by blanking unused PRRs with blank bitstreams. For PR blanking of a region to provide an energy saving, it is required that [6]:…”

Section: Partial Reconfigurationmentioning

confidence: 99%

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq

Vipin

Fahmy

2014

IEEE Embedded Syst. Lett.

104

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“…A higher number of active PEs results in increased throughput quality at the expense of increased power consumption. On the other hand, blanking [22] of the PEs results in reduced power consumption while incurring output quality degradation. A runtime multi-objective GA approach is used in finding a pareto optimal set as described below, thus spanning throughput versus power optimization, and also soft-resilience against faults using an autonomous strategy based on a feedback arrangement.…”

Section: Power Consumptionmentioning

confidence: 99%

Power and quality-aware image processing soft-resilience using online multi-objective GAs

Imran

Ashraf

DeMara

2015

IJCVR

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A self-aware signal processing architecture is proposed based on adaptive resource escalation which is guided by a multi-objective Genetic Algorithm (GA). The GA prioritizes tasks within a reconfigurable hardware fabric to maintain the quality-of-service and power consumption objectives. Attainment of these objectives is subject to the intrinsic reliability and performance of the computational elements in the resource pool. A health metric at the application layer, such as Peak-Signal-to-Noise Ratio (PSNR) measurement in a Discrete Cosine Transform (DCT) or Measure of Confidence in a Support Vector Machine (SVM) classifier, is used to assess throughput performance. When performance decreases beyond acceptable tolerances, the primary objective is to maximally recover output quality. The secondary objective is to minimize power consumption which also depends upon the input signal characteristics, in addition to the utilized computational resources. An adaptive guidance function for GA-driven recovery is proposed and validated for these objectives. It retains healthy processing elements in the throughput datapath to gracefully-degrade throughput by optimizing resource selection.

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“…PDR enables the system to react dynamically to changes in the structure or performance and power constraints of the application, allowing it to address inefficiencies in the allocation of resources and more accurately implement changing software routines as dynamic hardware accelerators [35]. These circuits can then be easily removed or gated when they are no longer required to reduce power consumption [38]. PDR can also increase the performance of an FPGA based system because it permits the continued operation of portions of the dynamic region unaffected by reconfiguration tasks.…”

Section: Energy Efficiency Techniques In Reconfigurable Multi-corementioning

confidence: 99%

Energy Efficient Multi-Core Processing

Leech¹,

Kázmierski

2014

ELS

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Abstract-This paper evaluates the present state of the art of energy-efficient embedded processor design techniques and demonstrates, how small, variable-architecture embedded processors may exploit a run-time minimal architectural synthesis technique to achieve greater energy and area efficiency whilst maintaining performance. The picoMIPS architecture is presented, inspired by the MIPS, as an example of a minimal and energy efficient processor. The picoMIPS is a variablearchitecture RISC microprocessor with an application-specific minimised instruction set. Each implementation will contain only the necessary datapath elements in order to maximise area efficiency. Due to the relationship between logic gate count and power consumption, energy efficiency is also maximised in the processor therefore the system is designed to perform a specific task in the most efficient processor-based form. The principles of the picoMIPS processor are illustrated with an example of the discrete cosine transform (DCT) and inverse DCT (IDCT) algorithms implemented in a multi-core context to demonstrate the concept of minimal architecture synthesis and how it can be used to produce an application specific, energy efficient processor.

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On energy efficiency of reconfigurable systems with run-time partial reconfiguration

Cited by 18 publications

References 9 publications

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq

Power and quality-aware image processing soft-resilience using online multi-objective GAs

Energy Efficient Multi-Core Processing

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