2009
DOI: 10.1109/led.2009.2028907
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On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors

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Cited by 205 publications
(95 citation statements)
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“…The entire gate capacitance to fall upon the drain terminal (C GD % C GG ) in contrast to a MOSFET, where the total gate capacitance is known to be symmetrically distributed among the source and the drain terminal [51]. As a result of this enhanced Miller capacitance effect, a voltage spike or large overshoot appears on the transient plots of the TFET based inverters [34,55,56]. Careful observation of the inset of Fig.…”
Section: Resultsmentioning
confidence: 99%
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“…The entire gate capacitance to fall upon the drain terminal (C GD % C GG ) in contrast to a MOSFET, where the total gate capacitance is known to be symmetrically distributed among the source and the drain terminal [51]. As a result of this enhanced Miller capacitance effect, a voltage spike or large overshoot appears on the transient plots of the TFET based inverters [34,55,56]. Careful observation of the inset of Fig.…”
Section: Resultsmentioning
confidence: 99%
“…So far, TFETs are extensively investigated for low-power digital logic applications with very little attention given to analog/RF performance. Until now, there has been only a few studies [34][35][36] containing the analysis of the usage of TFETs for high frequency analog/mixed-signal applications. High gate-to-drain capacitance C GD and low value of transconductance are identified as the major area of concerns and challenges for use of TFETs in high frequency analog/RF applications.…”
Section: Introductionmentioning
confidence: 99%
“…In [13], the authors have shown that in comparison with Sibased TFETs, the design of TFETs with III-V materials (low bandgap and low mass ) can mitigate the Miller capacitance effect due to the reduced density of states (DOS) of such materials. Therefore, TFETs designed with III-V materials are advantageous in comparison with Silicon devices for ultra-low power applications focused on energy-harvesting.…”
Section: Tunnel Fet Intrinsic Capacitancementioning
confidence: 99%
“…4 (a), the total gate capacitance of the heterojunction TFET is dominated by CGD. As the TFET current is dependent on the barrier shrinking in the sourcechannel interface, the resulting CGS is shown much lower than CGD when the transistor is active [13,14] The lower gate-capacitance of TFETs in comparison with Si MOSFETs can reduce the dynamic power consumption and delays of digital circuits as shown in [15]. In digital logic, the uni-directional conduction of TFET devices and the enhanced Miller capacitance can result in bootstrapped nodes within the circuit, causing potential failures and reliability risks [15,16].…”
mentioning
confidence: 99%
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