On-Fly Offset-Correction Method for High-Speed Comparators using All-Digital Phase Measurement

Amaya, Andres; Roa, Elkim

doi:10.1109/iscas.2018.8351268

Cited by 3 publications

(1 citation statement)

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“…As a result, PORT paves the way to eliminate the necessity of the alternative signal path. Partial work has been reported by the authors in a brief paper [6]. This work features new content that includes: (1) a detailed description of the technique's operation and its integration in a DFE topology, (2) a new approach for residual offset analysis and minimisation, (3) extended and exhaustive measurement results obtained through the chip‐scope technique, and (4) algorithm proposals to improve measurement performance.…”

Section: Introductionmentioning

confidence: 99%

A digital phase‐based on‐fly offset compensation method for decision feedback equalisers

Amaya

Ardila

Roa

2021

IET Circuits, Devices & Syst

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A low-complexity method to reduce the offset voltage of dynamic comparators employed as samplers in decision feedback equalisers (DFE) is introduced. The authors propose the phase-domain offset reduction technique (PORT), which leverages an all-digital phase estimation of output data for offset compensation, without setting the comparator input to a common-mode voltage (V CM). While traditional techniques might break the data link for offset adjustment, the proposed technique allows calibrating the comparator on-thefly. Measurements from a 26-dB-loss on-chip emulated channel with chip-scope capability validates PORT through eye-diagrams at sampler input. A prototype was implemented in a TSMC 130 nm 1.2 V process, and experimental results show the possibility of extending PORT to state-of-the-art technology nodes for multi-gigabit operation. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Introductionmentioning

confidence: 99%