On Mathematical Models of Optimal Video Memory Design

Xu, Yihuan; Das, Hritom; Gong, Yifu; Gong, Na

doi:10.1109/tcsvt.2018.2890383

Cited by 11 publications

(3 citation statements)

References 17 publications

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“…Memristors are potential candidates to address these issues. Memristors have proven to be more compact and power efficient for synaptic implementation compared to SRAM 21 and capacitor-based implementations of the same resolutions 9 , 22 . Memristive synapses have also been shown to have extended memory retention time 22 – 24 .…”

Section: Introductionmentioning

confidence: 99%

Enhanced read resolution in reconfigurable memristive synapses for Spiking Neural Networks

Das,

Schuman,

Chakraborty

et al. 2024

Sci Rep

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The synapse is a key element circuit in any memristor-based neuromorphic computing system. A memristor is a two-terminal analog memory device. Memristive synapses suffer from various challenges including high voltage, SET or RESET failure, and READ margin issues that can degrade the distinguishability of stored weights. Enhancing READ resolution is very important to improving the reliability of memristive synapses. Usually, the READ resolution is very small for a memristive synapse with a 4-bit data precision. This work considers a step-by-step analysis to enhance the READ current resolution or the read current difference between two resistance levels for a current-controlled memristor-based synapse. An empirical model is used to characterize the $${\hbox {HfO}}_{2}$$ HfO 2 based memristive device. $$1\textrm{st}$$ 1 st and $$2\textrm{nd}$$ 2 nd stage device of our proposed synapse design can be scaled to enhance the READ current margin up to $$\sim$$ ∼ 4.3$$\times$$ × and $$\sim$$ ∼ 21%, respectively. Moreover, READ current resolution can be enhanced with run-time adaptation techniques such as READ voltage scaling and body biasing. The READ voltage scaling and body biasing can improve the READ current resolution by about 46% and 15%, respectively. TENNLab’s neuromorphic computing framework is leveraged to evaluate the effect of READ current resolution on classification, control, and reservoir computing applications. Higher READ current resolution shows better accuracy than lower resolution even when facing different levels of read noise.

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Section: Introductionmentioning

confidence: 99%

Enhanced read resolution in reconfigurable memristive synapses for Spiking Neural Networks

Das,

Schuman,

Chakraborty

et al. 2024

Sci Rep

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“…This is because, although mobile videos are delivered over different networks and are visualized in various mobile terminals, there are three common characteristics that may potentially contribute to low-power design [5]: (i) Inputs: video data is noisy and redundant; (ii) Outputs: videos on mobile devices are generated for humans such that minor variations cannot be discerned; and (iii) Computation Patterns: statistical computations during the video data processing results in attenuation or cancellation of errors, which can potentially fix faults caused by memory failures. Utilizing these intrinsic characteristics of mobile video applications, such as the contribution of different bits of pixels to output quality, different approximate memories with optimized design techniques (e.g., memory cell structures [1], [6], device sizing [7], or error-correction code (ECC) [8], [9]) are used VOLUME 11, 2023 This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.…”

Section: Introductionmentioning

confidence: 99%

Approximate Memory for Low-Power Video Applications

et al. 2023

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In this paper, an error-correction code (ECC)-enabled memory design with selective bit hardening is proposed for approximate data storage. Approximate memory is suitable for errortolerant applications, and can achieve low-power design goals within targeted quality. Our design offers approximately 90% power savings compared to traditional memory, without compromising perceived quality. To the best of our knowledge, combining selective bit hardening with ECC is a novel approach to ensure the protection of MSBs and protect other faulty bits, respectively. Our proposed method requires no area overhead for MSB hardening, other than one additional input pin; and area overhead for implementing ECC is minimal.INDEX TERMS Approximate memory, videos, error-correction code (ECC), memory, power consumption, video quality, power-quality trade-off, and bit hardening.

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“…To resolve this issue, heterogeneous sized 6T SRAM architecture is proposed in [7], where only 6T SRAM cells are used for different bits of a pixel but with different area. HOBs of pixels require relatively larger cells area as compared to the LOBs as SRAM cell having larger area has lower BER [6, 7, 15]. LOBs are designed with smaller cells area to get the area benefit.…”

Section: Introductionmentioning

confidence: 99%