On multiple slice turbo codes

Gnaedig, David; Boutillon, Emmanuel; Jézéquel, Michel; Gaudet, Vincent; Gulak, P.G.

doi:10.1007/bf03219808

Cited by 13 publications

(3 citation statements)

References 9 publications

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“…In [7], the authors propose a deterministic methodology to design collision-free interleavers. In [8] and [6] the authors define collision-free permutations thanks to a combination of a spatial and a temporal permutation. The authors of [9] simply integrate the collision-free constraint in the design of their interleaver.…”

Section: Related Workmentioning

confidence: 99%

“…1 (Static Address Generation Easing) dedicated to the memory 1 Patent pending in France & UE n°0754793 and patent pending in USA n°20090031094: C.Chavet, P.Coussy, P.Urard, E.Martin, "Apparatus for data interleaving algorithm" mapping in block-based and parallel interleaver architectures. Counter to previous work, the proposed method considers both the generation of a conflict-free in-place memory mapping for any interleaving law (as well as [13] or [1]) and it is able to optimize the interconnection network (as well as [8]) in order to target a specific steering component to compose an optimized interconnection network between the PEs and the memory banks (if the interleaving rule enables to use this steering component, e.g. a barrel-shifter, a butterfly…).…”

Section: Related Workmentioning

confidence: 99%

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Static Address Generation Easing: a design methodology for parallel interleaver architectures

Coussy

Urard

Martin

2010

2010 IEEE International Conference on Acoustics, Speech and Signal Processing

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For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper we propose a methodology which finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture. Finally, we show through a pedagogical example the interest of our approach compared to state-of-the-art techniques.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Static Address Generation Easing: a design methodology for parallel interleaver architectures

Coussy

Urard

Martin

2010

2010 IEEE International Conference on Acoustics, Speech and Signal Processing

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“…However, in a parallel decoder during the scrambled half iteration collisions can occur, namely more SISOs could need to access the same memory during the same cycle. Since the collision phenomenon increases ID cyc oh , several algorithmic approaches to design collision free interleavers [Giulietti et al 2002]; [Kwak & Lee, 2002]; [Gnaedig et al, 2003]; [Tarable et al, 2004] have been proposed. On the other hand, architectures to manage collisions in a parallel turbo decoder have also been proposed in the literature [Thul et al, 2002]; [Gilbert et al, 2003]; [Thul et al, 2003]; [Speziali & Zory, 2004]; [Martina et al 2008-a]; [Martina et al, 2008-b], in particular [Martina et al 2008-b] deals with the parallelization of the WIMAX CTC interleaver and avoids collision by the means of a throughput/parallelism scalable architecture that features ID cyc oh =0.…”

Section: Sp Imentioning

confidence: 99%

VLSI Architectures for WIMAX Channel Decoders

Martina¹,

Masera²

2009

WIMAX New Developments

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SPC05-3: On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference

Müller

Baghdadi

Jézéquel³

2006

IEEE Globecom 2006

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In forward error correction, convolutional turbo codes were introduced to increase error correction capability approaching the Shannon bound. Decoding of these codes, however, is an iterative process requiring high computation rate and latency. Thus, in order to achieve high throughput and to reduce latency, crucial in emerging digital communication applications, parallel implementations become mandatory. This paper explores and analyses existing parallelism techniques in convolutional turbo decoding with the BCJR algorithm. For component-decoder parallelism, we illustrate the influence of interleaving scheme and we propose new interleaving rules allowing to maximize parallelism efficiency.

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On multiple slice turbo codes

Cited by 13 publications

References 9 publications

Static Address Generation Easing: a design methodology for parallel interleaver architectures

Static Address Generation Easing: a design methodology for parallel interleaver architectures

VLSI Architectures for WIMAX Channel Decoders

SPC05-3: On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference

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