On/off wide tuning range voltage controlled ring oscillator for UWB pulse generator

Barraj, Imen; Neifar, Amel; Trabelsi, Hatem; Masmoudi, Mohamed

doi:10.1109/ssd.2016.7473729

Cited by 9 publications

(3 citation statements)

References 11 publications

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“…Fig. 6 (a) the higher FWHM pulse of 325 ps, according to (2), should present a -10 dB bandwidth of 2.25 GHz. As plotted in Fig.…”

Section: A B-uwb-pg Output Characterizationmentioning

confidence: 96%

“…Therefore, a time-gated oscillator is generally employed as UWB pulse generator [1]. In [2] a pulse generator based on voltage controlled oscillator (VCO) with tunable central frequency is proposed. Besides pulse position modulation (PPM), it is possible to use pulse amplitude modulation (PAM) where the pulse generator output amplitude is attenuated depending on the transmitting binary code [3].…”

Section: Introductionmentioning

confidence: 99%

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Ultra-Low-Jitter Fully Tunable Baseband Pulse Generator for UWB Applications

Garbati

Perret

Siragusa

et al. 2018

IEEE Trans. Microwave Theory Techn.

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This paper presents a fully tunable baseband ultrawideband (UWB) pulse generator, realized with commercial offthe-shelf components (COTS). It is made of high speed logic gates and comparators, and it is compliant with current mode logic (CML) digital standard. The pulse emitted power and bandwidth are tunable with pulse-width and amplitude variation, which shows high flexibility. This advantage simplifies the design of the downstream shaping network, as so to be compliant with international regulations. A differential output with very low jitter, and high pulse repetition frequency (PRF) is demonstrated.

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“…Fig. 6 (a) the higher FWHM pulse of 325 ps, according to (2), should present a -10 dB bandwidth of 2.25 GHz. As plotted in Fig.…”

Section: A B-uwb-pg Output Characterizationmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%

Ultra-Low-Jitter Fully Tunable Baseband Pulse Generator for UWB Applications

Garbati

Perret

Siragusa

et al. 2018

IEEE Trans. Microwave Theory Techn.

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“…Therefore RO is a good choice, since it possesses wider tuning range and smaller die area [16]. On the other hand, owing to the ease of integration and compatibility with the digital CMOS process, ROs are extensively demanded in recent years [17].…”

Section: Proposed Non‐redundant Delay Cellmentioning

confidence: 99%

Fault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology

Salem

Zandevakili

Mahani

et al. 2018

IET Circuits, Devices & Systems

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A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault-tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm 2 chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non-redundant RO s.

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