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Resistive ternary content addressable memories (Re-TCAMs) are considered a potential platform for in-memory associative processing. Re-TCAM permits the store and process of the data in the same physical area, allowing inmemory computing. Given the unique properties of the non-volatile memristive device, Re-TCAM is capable of low search energy, large-scale storage, and massively parallel processing. However, like any other semiconductor, memristor as a nanodevice suffers from fabrication process imperfections that provoke a significant variance in their high (R H) and low (R L) resistance states. These variations might lead to the malfunction of the Re-TCAM array and affect its performance and reliability. This paper proposes a simplified mathematical formulation of the memristor state variability for 2T2M bit-cell-based Re-TCAM array. We present a comprehensive statistical design, considering different circuit parameters and variance effects, such as tolerance of memristance variation, the memristor ratio (α = R H =R L), transistor technology, and memory width. The impact of these parameters on the performance is formulated as the probability of error is extensively studied, and a closed-form expression for the optimal threshold voltage is derived. The utility of the presented investigation is illustrated using a design example with real device parameters.

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