On Overflow Detection and Correction in Digital Filters

Landauro, A.; Liénard, Joêl

doi:10.1109/t-c.1975.224168

Cited by 3 publications

(1 citation statement)

References 2 publications

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“…Previous research on overflow detection and saturation has focused on fractional operands [14], [17] or operations other than multiplication [18], [19]. The main difference between fractional and integer multiplication is that fractional multiplication typically returns the most significant bits of the product.…”

Section: Introductionmentioning

confidence: 99%

Integer multiplication with overflow detection or saturation

Schuite

Balzola

Akkaş

et al. 2000

IEEE Trans. Comput.

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ÐHigh-speed multiplication is frequently used in general-purpose and application-specific computer systems. These systems often support integer multiplication, where two n-bit integers are multiplied to produce a Pn-bit product. To prevent growth in word length, processors typically return the n least significant bits of the product and a flag that indicates whether or not overflow has occurred. Alternatively, some processors saturate results that overflow to the most positive or most negative representable number. This paper presents efficient methods for performing unsigned or two's complement integer multiplication with overflow detection or saturation. These methods have significantly less area and delay than conventional methods for integer multiplication with overflow detection or saturation.

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Section: Introductionmentioning

confidence: 99%

Integer multiplication with overflow detection or saturation

Schuite

Balzola

Akkaş

et al. 2000

IEEE Trans. Comput.

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Prefilter, digital filter, and postfilter: Frequency response and spurious outputs

Pierre

1977

Computers & Electrical Engineering

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High Data Rate Filter Design for Satellite Communication

Sharma

Kulkarni

Pujari

et al. 2007

2007 3rd International Conference on Recent Advances in Space Technologies

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The choice of filter structure for any system depends Using IFIR filter, the same demodulator can be used for those on the various parameters like computational complexity, applications. The paper describes one of the applications of memory requirement, frequency of operation and finite world IFIR filter in realizing the 500Kbps BPSK demodulator. length effect. To overcome the limitations of Infinite Impulse In first section general design of an IFIR filter is discussed Response (IIR) filter, an Interpolated Finite Impulse Filter (IFIR) followed by description of an IR filter. i next section Costas has been designed and implemented in Xilinx FPGA. The paper Loop by demodlator is an witesIn equation FPGa deals with issues related to the hardware implementation & ways Loop BPSK demodulator is dealt with design equation. FPGA to increase operating frequency of filter. The paper compares the implementation of IFIR, IR and demodulator based on these suitability of different types of filters for satellite communication. filter is discussed afterwards. Finally comparison tables and It also describes the application of IFIR filter in high data rate results of implementation are presented.Binary Phase Shift Keying (BPSK) demodulator for satellite

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On Overflow Detection and Correction in Digital Filters

Cited by 3 publications

References 2 publications

Integer multiplication with overflow detection or saturation

Integer multiplication with overflow detection or saturation

Prefilter, digital filter, and postfilter: Frequency response and spurious outputs

High Data Rate Filter Design for Satellite Communication

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