Squaring is an important operation in digital signal processing applications. For several applications, a significant reduction in area, delay, and power consumption is achieved by performing squaring using specialized squarers, instead of multipliers. Although most previous reseafchbn parallel squarers focuses on the design of unsigned squarers, squaring of two's complement numbers is also often required. This paper presents the design ofparalle1 squarers that perform either unsigned or two's complement squaring, based on an input control signal. Compared to unsigned parallel squarers, these squarers require only a small amount of additional delay and area.

In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation.

ÐHigh-speed multiplication is frequently used in general-purpose and application-specific computer systems. These systems often support integer multiplication, where two n-bit integers are multiplied to produce a Pn-bit product. To prevent growth in word length, processors typically return the n least significant bits of the product and a flag that indicates whether or not overflow has occurred. Alternatively, some processors saturate results that overflow to the most positive or most negative representable number. This paper presents efficient methods for performing unsigned or two's complement integer multiplication with overflow detection or saturation. These methods have significantly less area and delay than conventional methods for integer multiplication with overflow detection or saturation.

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