Combined unsigned and two's complement squarers

Abstract

Squaring is an important operation in digital signal processing applications. For several applications, a significant reduction in area, delay, and power consumption is achieved by performing squaring using specialized squarers, instead of multipliers. Although most previous reseafchbn parallel squarers focuses on the design of unsigned squarers, squaring of two's complement numbers is also often required. This paper presents the design ofparalle1 squarers that perform either unsigned or two's complement squaring, based on an input control signal. Compared to unsigned parallel squarers, these squarers require only a small amount of additional delay and area.

Linear and Quadratic Interpolators Using Truncated-Matrix Multipliers and Squarers

“…Figure 2 shows a 12-bit truncated squarer. Truncated squarers are an extension of specialized squarers, which are described in [25]. As with truncated multipliers, r denotes the number of unformed columns, and k denotes the number of columns that are formed, but discarded in the final result.…”

A Low Power High Performance Radix-4 Approximate Squaring Circuit

“…Approximate squaring circuits have numerous applications as mentioned in [12][13][14][15]20] such as cryptography, computation of Euclidean distance among pixels for a graphics processor or in rectangular to polar conversions in several signal processing circuits where full precision results are not required. As indicated in [14,25], customized squaring modules do have important applications in digital signal processing.…”

“…This property has been investigated to provide optimizations in multiplier design at the bit level [18,19]. The design focusing on a squaring circuit employing this symmetry was proposed in [21], and numerous studies optimizing binary squaring circuits appear in [12][13][14][15]20]. These designs primarily optimize by using hardwired bit product arrangements to reduce array sizes for efficient accumulation, mostly focusing on low precision.…”

Efficient unsigned squarer design techniques

“…The folding technique described in [1] uses the symmetry of the partial product matrix (PPM) of squarer to archive 50% reduction of the number of partial products compared with a standard multiplier. The partial products rearrangement technique in [2,3] is used to reduce the total number of partial product bits and the depth of PPM.…”