On product overlay characterization after stressed layer etch

Haren, Richard van; Mouraille, Orion; Yildirim, Oktay; Dijk, Leon van; Kumar, Kaushik; Feurprier, Yannick; Hermans, Jan

doi:10.1117/12.2584311

Cited by 3 publications

(6 citation statements)

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“…At the next exposure step, if the top layer is exposed without proper correction, the resultant grid mismatch is translated into the layer-to-layer overlay error. Such grid distortion induced overlay error was reported in prior studies 4 , 5 . Stobert et al 6 .…”

Section: Introductionsupporting

confidence: 71%

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Predictive compact model for stress-induced on-product overlay correction

Zhang

Tabery

Maas

et al. 2022

J. Micro/Nanopattern. Mats. Metro.

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On-product overlay (OPO) is an important indicator of device yield. In this work, we show that stressed thin films used in semiconductor manufacturing can be an important contributor to OPO at multiple length scales. Depending on the stress level, film thickness, and the mask design, the overlay impact can be a few nanometers for the exposure of the next lithography layer. A predictive compact model based on pattern density is developed to accurately predict this overlay impact. The model is then verified using short-loop dual damascene wafers with stress split. The predictive model opens a new opportunity for model-based mask correction during optical proximity correction to increase the overlay margin for subsequent lithography exposures.

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Section: Introductionsupporting

confidence: 71%

“…Such grid distortion induced overlay error was reported in prior studies. 4,5 Stobert et al 6 proposed model-based correction during mask tape out flow on limited use cases. However, these studies did not address the mechanism of the short length scale local grid distortions and their link to wafer scale fingerprints.…”

Section: Introductionmentioning

confidence: 99%

Predictive compact model for stress-induced on-product overlay correction

Zhang

Tabery

Maas

et al. 2022

J. Micro/Nanopattern. Mats. Metro.

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“…This length scale corresponds to die level which repeats at each exposure field where we have reported an extensive study on both etch-induced [7,9] and stress related intra-field overlay [10]. Interestingly, the etch-induced intra-field overlay fingerprints were similar for wafers at different stress types and levels including no stress [7,9,10]. The common part was the Spin-On-Glass (SOG) anti-reflecting coating layer.…”

Section: Introductionmentioning

confidence: 95%

“…Despite the continuous improvements on scanner side, due to tighter requirements, handling high spatial frequency overlay penalties at small length scales (sub-mm level) becomes more challenging [8]. This length scale corresponds to die level which repeats at each exposure field where we have reported an extensive study on both etch-induced [7,9] and stress related intra-field overlay [10]. Interestingly, the etch-induced intra-field overlay fingerprints were similar for wafers at different stress types and levels including no stress [7,9,10].…”

Section: Introductionmentioning

confidence: 99%

Improving the on-product overlay performance after optimization of the etch-induced contributions

Yildirim,

van Haren,

Mouraille

et al. 2023

38th European Mask and Lithography Conference (EMLC 2023)

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“…For example, IC manufacturing steps like thin film deposition, etching and annealing may induce non-uniform stress variations over the wafer and within the exposure field. This can lead to in-plane distortions (IPD) that may have an impact on the layer-to-layer overlay performance [1][2]. Furthermore, process steps like Chemical Mechanical Planarization (CMP) can produce topography defects, which may lead to focus issues [3].…”

Section: Introductionmentioning

confidence: 99%

Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay

Balan

Michel

Mendes

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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In the field of semiconductor manufacturing, the precise alignment of patterns on a wafer die is critical for the proper functioning of the resulting integrated circuit. However, various factors can cause deformation of the die, which can result in overlay errors and negatively impact device performance. In this work, we focused on the development of die nanotopography metrology, which is used to investigate the topography evolution of five selected dies over several process steps. The impact of manufacturing steps as film deposition, annealing and CMP on die shape deformation and its relation to different pattern densities is measured using optical interferometry. We show that full-die nano-topography measurements are able to detect stress-induced in-plane die distortions as an effect of different annealing processes on SOI or silicon-bulk substrates.

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On product overlay characterization after stressed layer etch

Cited by 3 publications

References 0 publications

Predictive compact model for stress-induced on-product overlay correction

Predictive compact model for stress-induced on-product overlay correction

Improving the on-product overlay performance after optimization of the etch-induced contributions

Die-level nano-topography metrology to characterize the stress-induced in-plane distortion contribution to overlay

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