While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS. In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFET with the physical gate length being aggressively shrunk down to 10nm and the fin width down to 12nm. These MOSFETs are believed to be the smallest double-gate transistors ever fabricated. Excellent short-channel performance is observed in devices with a wide range of gate lengths (10~105nm). The subthreshold slopes of the 10nm gate length FinFETs are 125mV/dec for n-FET and 101mV/dec for p-FET, respectively. The DIBL's are 71mV/V for n-FET and 120mV/V for p-FET, respectively. At 55nm gate length, the subthreshold slopes are 64mV/dec for n-FET and 68mV/dec for p-FET, which is very close to the ideal MOSFET behavior (at room temperature). The DIBL's are 11mV/V for n-FET and 27mV/V for p-FET, respectively. All measurements were performed at a supply voltage of 1.2V. The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs. Due to the (110) channel crystal orientation, hole mobility in the fabricated p-channel FinFET remarkably exceeds that in a traditional planar MOSFET. At 105nm gate length, pchannel FinFET shows a record-high transconductance of 633µS/µm at a V dd of 1.2V. At extremely small gate lengths, parasitic R sd in the narrow fin (proportionally scaled with L g ) influences the device performance. Working CMOS FinFET inverters are also demonstrated.

In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

We describe methods to determine transfer functions for line edge roughness (LER) from the photoresist pattern through the etch process into the underlying substrate. Both image fading techniques and more conventional focus-exposure matrix methods may be employed to determine the dependence of photoresist LER on the image-log-slope (ILS) or resist-edge-log-slope (RELS) of the aerial image. Post-etch LER measurements in polysilicon are similarly correlated to the ILS used to pattern the resist. From these two relationships, a transfer function may be derived to quantify the magnitude of LER that transfers into the polysilicon underlayer from the photoresist. 1 A second transfer function may be derived from power spectral density (PSD) analysis of LER. This approach is desirable based on observations of pronounced etch smoothing of roughness in specific spatial frequency ranges.Smoothing functions and signal averaging of large numbers of line edges are required to partially compensate for large uncertainties in fast-Fourier transform derived PSDs of single line edges. An alternative and promising approach is to derive transfer functions from PSDs estimated using autoregressive algorithms.The utility of these methods to several photoresist and etch processes will be described.

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