On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling

As an alternative approach, analyzing hybrid property, the formal method using extended PSL to express specification of mixed-signal circuits is addressed in this paper. With the ability to modeling discrete and continuous dynamic system, Hybrid Automata is adopted in verification of mixed-signal circuits. We extend the PSL to HAPSL (Hybrid Automata Based PSL) with Hybrid Automata, and define EBNF grammar for the syntax of HAPSL. The continuous temporal property and probabilistic property of mixed-signal circuit can be abstracted by HAPSL. Model Checking is proposed as a formal verifying methodology, in which an onthe-jly checking is preformed for the continuous temporal property, and the checking ofprobabilistic property is based on hypothesis test. We illustrated this method by analyzing two mixed-signal circuits. The specification ofcircuit that depends on continuous variables and stochastic process is expressed by HAPSL sentences.

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“…PSL has been wildly used in the verification of logical system [4] [5]. PSL has also been established as IEEE 1850 standard [3] [6].…”

Section: Introductionmentioning

confidence: 99%

Formal verification of mixed-signal circuits using extended PSL

Zhang

Gao

Fan

2009

2009 IEEE 8th International Conference on ASIC

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“…Some techniques have been proposed in the past to check the correctness of the topdown refinement flow [4,5]. In [4], properties expressed at TLM are reused at RTL by means of transactors. Thus, the behavior expressed by the set of reusable properties can be checked also in the refined version of the design.…”

Section: Introductionmentioning

confidence: 99%

“…In [5], an incremental verification based on assertions is proposed to validate the TLM-to-RTL design refinement. The concept of equivalence proposed in [4,5] is based on properties, i.e., two implementations are equivalent if they satisfy the same set of properties. Thus, the effectiveness of such a kind of equivalence checking depends on the quality of the defined properties, since the equivalence is guaranteed only for behaviors for which a property has been defined.…”

Section: Introductionmentioning

confidence: 99%

Towards Equivalence Checking Between TLM and RTL Models

Bombieri

Fummi

Pravadelli

et al. 2007

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)

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“…In fact, in spite of its name, transaction level does not denote a single level of description. Rather, it refers to a group of three abstraction levels: level 1 (the lowest), level 2, and level 3 (the highest), each varying in the degree of expressible functional and temporal details [8].…”

Section: Introductionmentioning

confidence: 99%

On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL

Bombieri

Fummi

Pravadelli

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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Transaction level modeling (TLM) is becoming an usual practice for simplifying system-level design and architecture exploration. It allows the designers to focus on the functionality of the design, while abstracting away implementation details that will be added at lower abstraction levels. However, moving from transaction level to RTL requires to redefine TLM testbenches and assertions. Such a wasteful and error prone conversion can be avoided by adopting transactor-based verification (TBV). Many recent works adopt this strategy to propose verification methodologies that allow (1) mixing TLM and RTL components, and (2) reusing TLM assertions and testbenches at RTL. Even if practical advantages of such an approach are evident, there are no papers in the literature that evaluate the effectiveness of the TBV compared to a more traditional RTL verification strategy. This paper is intended to fill in the gap. It theoretically compares the quality of the TBV towards the rewriting of assertions and testbenches at RTL with respect to both fault coverage and assertion coverage.

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On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling

Abstract: In this paper we present some key concepts concerning the Properties Specification Language (PSL)

Cited by 17 publications

References 7 publications

Formal verification of mixed-signal circuits using extended PSL

Formal verification of mixed-signal circuits using extended PSL

Towards Equivalence Checking Between TLM and RTL Models

On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL

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