On re-composition of motion compensated macroblocks for DCT-based video transcoding

Fung, Kai-Tat; Siu, Wan-Chi

doi:10.1016/j.image.2005.06.004

Cited by 3 publications

(2 citation statements)

References 19 publications

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“…The control signals are also used to select the correct sign in the operations executed by PEs. The PEs from the cycle and pseudo-cycle convolution modules, that represent the hardware core of the VLSI architecture, execute the operations from relation (6).…”

Section: Hardware Realization Of the Vlsi Algorithmmentioning

confidence: 99%

“…The discrete cosine transform (DCT) and discrete sine transform (DST) [1][2][3] are key elements in many digital signal processing applications being good approximations to the statistically optimal Karhunen-Loeve transform [2,3]. They are used especially in speech and image transform coding [3,4], DCT-based subband decomposition in speech and image compression [5], or video transcoding [6]. Other important applications are: block filtering, feature extraction [7], digital signal interpolation [8], image resizing [9], transform-adaptive filtering [10,11], and filter banks [12].…”

Section: Introductionmentioning

confidence: 99%

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Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT

Chiper

Ungureanu

2010

EURASIP J. Adv. Signal Process.

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Using a specific input-restructuring sequence, a new VLSI algorithm and architecture have been derived for a high throughput memory-based systolic array VLSI implementation of a discrete cosine transform. The proposed restructuring technique transforms the DCT algorithm into a cycle-convolution and a pseudo-cycle convolution structure as basic computational forms. The proposed solution has been specially designed to have good fixed-point error performances that have been exploited to further reduce the hardware complexity and power consumption. It leads to a ROM based VLSI kernel with good quantization properties. A parallel VLSI algorithm and architecture with a good fixed point implementation appropriate for a memory-based implementation have been obtained. The proposed algorithm can be mapped onto two linear systolic arrays with similar length and form. They can be further efficiently merged into a single array using an appropriate hardware sharing technique. A highly efficient VLSI chip can be thus obtained with appealing features as good architectural topology, processing speed, hardware complexity and I/O costs. Moreover, the proposed solution substantially reduces the hardware overhead involved by the pre-processing stage that for short length DCT consumes an important percentage of the chip area.

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Section: Hardware Realization Of the Vlsi Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT

Chiper

Ungureanu

2010

EURASIP J. Adv. Signal Process.

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Realization of Systolic Architecture of Discrete Cosine Transform

Jain

2021

2021 International Conference on Computer Communication and Informatics (ICCCI)

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On the architecture of H.264 to H.264 homogeneous transcoding platform

Siu

Kam

Hui

et al. 2008

2008 International Conference on Neural Networks and Signal Processing

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-For homogeneous transcoding, we usually transfer a compressed video into a lower bit-rate and/or video with a smaller size. In this paper we introduce the general architecture of a downing sizing transcoder and propose some novel techniques for its practical realization, including motion vector re-estimation, sub-pixel motion re-estimation, mode redecision, etc. We then generalize the idea of transcoding to video enlargement and propose a simple framework for its reencoding. The paper ends with some useful remarks on the formation of super-resolution videos via the transcoder frame work.

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On re-composition of motion compensated macroblocks for DCT-based video transcoding

Cited by 3 publications

References 19 publications

Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT

Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT

Realization of Systolic Architecture of Discrete Cosine Transform

On the architecture of H.264 to H.264 homogeneous transcoding platform

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