Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256) 2001
DOI: 10.1109/acssc.2001.987047
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On signal-gating schemes for low-power adders

Zhijun Huang1,
M.D. Ercegovac2
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Cited by 4 publications
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References 19 publications
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Low power FPGA-based implementation of decimating filters for multistandard receiver

Khouja
1
,
Grati
2
,
Ghazel
3
2006
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.
6
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Low power FPGA-based implementation of decimating filters for multistandard receiver

Khouja
1
,
Grati
2
,
Ghazel
3
2006
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.
6
0
1
0
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Precomputation-based guarding for dynamic and leakage power reduction

Abddollahi
1
,
Pedarm
2
,
Fallah
3
et al.
Proceedings 21st International Conference on Computer Design
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Low Power Implementation of Decimation Filters in Multistandard Radio Receiver Using Optimized Multiplication-Accumulation Unit

Khouja
1
,
Grati
2
,
Ghazel
3
2007
2007 14th IEEE International Conference on Electronics, Circuits and Systems
1
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