Low power FPGA-based implementation of decimating filters for multistandard receiver

Khouja, Nadia; Grati, Khaled; Ghazel, Adel

doi:10.1109/dtis.2006.1708728

Cited by 6 publications

(1 citation statement)

References 17 publications

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“…On the other hand, one of the advantages in BSSP is that the decimator and interpolator for the conventional Nyquist approach are not required. Depending on applications, the hardware resources for a decimator can be as low as 556 LUTs as in [9] or 2116 Virtex-4 slices as in [10]. As one decimator is required for each analog input and one interpolator is required for each analog output, the total amount of FPGA resources for decimator and interpolator can be large.…”

Section: Discussionmentioning

confidence: 99%

Quad-level bit-stream signal processing on FPGAs

Ng¹,

Wong²,

So³

2008

2008 International Conference on Field-Programmable Technology

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Quad-level bit-stream signal processing (BSSP) circuits are implemented and their performances are compared with previously published tri-level and bi-level BSSP implementations on FPGAs. BSSP refers to the process of performing computation directly on over-sampled delta-sigma modulated signals to eliminate the need of resource consuming decimators and interpolators. Quadlevel BSSP offers better performance than their biand tri-level counterparts at the expense of higher resource utilization. Using a digital phase locked loop (DPLL) and a quadrature phase-shift keying (QPSK) demodulator as application examples, the effectiveness of quad-level BSSP on FPGAs is studied. The BSSP approach will be contrasted with conventional multi-bit implementations using built-in digital signal processing blocks in modern FPGAs.

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Section: Discussionmentioning

confidence: 99%