Quad-level bit-stream signal processing on FPGAs

Abstract

Quad-level bit-stream signal processing (BSSP) circuits are implemented and their performances are compared with previously published tri-level and bi-level BSSP implementations on FPGAs. BSSP refers to the process of performing computation directly on over-sampled delta-sigma modulated signals to eliminate the need of resource consuming decimators and interpolators. Quadlevel BSSP offers better performance than their biand tri-level counterparts at the expense of higher resource utilization. Using a digital phase locked loop (DPLL) and a quadrature phase-shift keying (QPSK) demodulator as application examples, the effectiveness of quad-level BSSP on FPGAs is studied. The BSSP approach will be contrasted with conventional multi-bit implementations using built-in digital signal processing blocks in modern FPGAs.

On IIR‐based bit‐stream multipliers

“…As shown in [27], tri-and quad-level BSSP blocks provide higher performance at the expense of higher hardware complexity. This section details the designs and tradeoffs of the tri-and quad-level IIR-based bit-stream multipliers.…”

“…The design of sigma-delta-based IIR LPFs has been well studied [25]. In this implementation, we apply the tri-and quad-level IIR LPF and DSDM designs described in [27]. In Figure 1, the two-point moving average filter design C implements the following equation: As a result, the entire combination of moving average and multiplication can be implemented by a single multiplexer as shown in Figure 5, wherein the values −1 and 1 are represented by 0 and 1, respectively.…”

“…With the key design parameter determined as in Section 3, we are now in the position to extend the original bi-level IIR-based bit-stream multiplier to its tri-and quad-level counterparts. As shown in [27], tri-and quad-level BSSP blocks provide higher performance at the expense of higher hardware complexity. This section details the designs and tradeoffs of the tri-and quad-level IIR-based bit-stream multipliers.…”

“…The design of sigma-delta-based IIR LPFs has been well studied [25]. In this implementation, we apply the tri-and quad-level IIR LPF and DSDM designs described in [27]. In Figure 1, the two-point moving average filter design C implements the following equation:…”