On test time reduction using pattern overlapping, broadcasting and on-chip decompression

Chloupek, Martin; Novák, Ondřej; Jenicek, Jiri

doi:10.1109/ddecs.2012.6219078

Cited by 12 publications

(7 citation statements)

References 25 publications

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“…The equations for calculating the number of inserted flipflops are shown in (7). The central position and feasible region for the flip-flop insertion are described in (8) and (9), respectively.…”

Section: Layout-aware Flip-flop Insertion For Si/so Pathsmentioning

confidence: 99%

“…Earlier approaches have presented several different methods for the compression of test vectors to reduce scan test application time by partitioning a single scan chain into a number of shorter scan chains. Methods for compressing test vectors require some additional on-chip hardware, such as a decompressor (before any scan chains) and a response compressor (after any scan chains) [6], [7]. Furthermore, layout-aware scan designs,…”

Section: Introductionmentioning

confidence: 99%

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Physical Aware Approaches for Speeding up Scan Shift Operation in SoC

Lee

Chang

Lee

et al. 2016

ETRI J

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System-on-chip (SoC) designs have a number of flipflops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operationaware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

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Section: Layout-aware Flip-flop Insertion For Si/so Pathsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Physical Aware Approaches for Speeding up Scan Shift Operation in SoC

Lee

Chang

Lee

et al. 2016

ETRI J

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show abstract

“…Reusable scan chains [16] and pattern overlapping [10] [11] eliminates unwanted scan chain operations by the use if patterns that resemble the previous pattern such that the number of scan shifting is minimum. Hence high reduction is achieved on availability of such patterns.…”

Section: Prior Workmentioning

confidence: 99%

Finding best voltage and frequency to shorten power-constrained test time

Venkataramani

Sindia

Agrawal

2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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Abstract-In a digital test, supply voltage (VDD), clock frequency (ftest), peak power (PMAX ) and test time (T T ) are related parameters. For a given limit PMAX = PMAXfunc, normally set by functional specification, we find the optimum VDD = VDDopt and ftest = fopt to minimize T T . A solution is derived analytically from the technology-dependent characterization of semiconductor devices. It is shown that at VDDopt the peak power any test cycle consumes just equals PMAXfunc and ftest is fastest that the critical path at VDDopt will allow. The paper demonstrates how test parameters can be obtained numerically from MATLAB, or experimentally by bench test equipment like National Instruments' ELVIS. This optimization can cut the test time of ISCAS'89 benchmarks in 180nm CMOS into half.

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“…Earlier approaches to reduce test time used pattern overlapping [12], [14] and reusable scan chains [18] to eliminate unwanted scan chain operations through similar patterns to reduce the scan shift process. Reduction in test time depends on the availability of such patterns.…”

Section: Prior Workmentioning

confidence: 99%

“…ASYNCHRONOUS CLOCK TEST Equation (12) shows that, for a given rated power P M AX(rated) , the total test time is a function of the maximum energy dissipated during test. At a constant power supply, the energy consumed during any cycle is a function of the amount of signal transitions in the CUT caused by the pattern applied.…”

Section: Test Time Reductionmentioning

confidence: 99%