2009
DOI: 10.1063/1.3180703
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On the 1/f noise of triple-gate field-effect transistors with high-k gate dielectric

Abstract: Articles you may be interested inImproved modeling of gate leakage currents for fin-shaped field-effect transistors Effect of channel positioning on the 1 ∕ f noise in silicon-on-insulator metal-oxide-semiconductor field-effect transistors Origin of the front-back-gate coupling in partially depleted and fully depleted silicon-on-insulator metal-oxidesemiconductor field-effect transistors with accumulated back gate Electron valence-band tunneling-induced Lorentzian noise in deep submicron silicon-on-insulator m… Show more

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Cited by 19 publications
(11 citation statements)
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“…However, microelectronic manufacturers are now facing serious issues like overheat, high stress and soon the fundamental miniaturization limit. Fortunately, several other solutions are investigated, such as new materials, [1][2][3][4] new structures, [5][6][7][8] etc. Among these, a new metal-oxidesemiconductor (MOS) field-effect transistor (FET) structure based on an accumulation layer instead of the conventional inversion one needs to be seriously considered as base for the future complementary MOS (CMOS).…”
Section: Introductionmentioning
confidence: 99%
“…However, microelectronic manufacturers are now facing serious issues like overheat, high stress and soon the fundamental miniaturization limit. Fortunately, several other solutions are investigated, such as new materials, [1][2][3][4] new structures, [5][6][7][8] etc. Among these, a new metal-oxidesemiconductor (MOS) field-effect transistor (FET) structure based on an accumulation layer instead of the conventional inversion one needs to be seriously considered as base for the future complementary MOS (CMOS).…”
Section: Introductionmentioning
confidence: 99%
“…[5][6][7][8][9][10] Extensive investigations of the Lorentzian components with temperature were reported recently, identifying the traps originating from process steps used for realization of the source and drain contacts and traps related to the process steps used for the channel optimization. 6,9 Regarding the 1/f noise, it has been ascribed to carrier number fluctuations (CNF) due to carrier exchange between the gate dielectric traps near the interface and the channel, [5][6][7][8] whereas the charge fluctuations in the gate dielectric can induce additional fluctuations of the carrier mobility, giving rise to the so-called correlated mobility fluctuations (CMF).…”
mentioning
confidence: 99%
“…ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 128.255.-148 31. Downloaded on 2015-07-14 to IP…”
mentioning
confidence: 99%