On the automatic integration of hardware accelerators into FPGA-based embedded systems

Pilato, Christian; Cazzaniga, Andrea; Durelli, Gianluca; Otero, Andrés; Sciuto, D.; Santambrogio, Marco D.

doi:10.1109/fpl.2012.6339218

Cited by 11 publications

(4 citation statements)

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“…For targeting such platform, we are implementing a C++ framework by merging and extending the ones proposed in [18] and [19]. In particular, with respect to [18], we are introducing the support for reconfiguration and the integration of cores generated by commercial tools or provided by hand. Indeed we defined a common interface (memory-mapped registers to exchange the parameters and memory interface to access the DDR2 SRAM) that has to be respected by all the cores to deal with the runtime manager.…”

Section: Target Platforms and Experimentsmentioning

confidence: 99%

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration

Papadimitriou

Pilato

Pnevmatikatos

et al. 2012

2012 IEEE 15th International Conference on Computational Science and Engineering

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Abstract-During the last few years, there is an increasing interest in mixing software and hardware to serve efficiently different applications. This is due to the heterogeneity characterizing the tasks of an application which require the presence of resources from both worlds, software and hardware. Controlling effectively these resources through an integrated tool flow is a challenging problem and towards this direction only a few efforts exist. In fact, a framework that seamlessly exploits both resources of a platform for executing efficiently an application has not yet come into existence. Moreover, reconfigurable computing often incorporated in such platforms due to its high flexibility and customization, has not yet taken off due to the lack of exploiting its full capabilities. Thus, the capability of reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) to be dynamically reconfigured, i.e. reprogramming part of the chip while other parts of the same chip remain functional, has not yet taken off even in small-scale basis. The inherent difficulty in using the tools to control this technology has kept it back from being adopted by academia and industry alike.The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a design methodology and a tool flow that will enable designers to implement effectively and easily a system specification on a platform combining software and reconfigurable resources. The FASTER framework accepts as input a high-level description of the application and the architectural details of the target platform, and through certain steps it can enable the full use of the capabilities of the platform, while at the same time it should be flexible enough so as to balance efficiently performance, power and area. One of the main novelties is the incorporation of partial reconfiguration as an explicit design concept at an early stage of the design flow. We target different applications from the embedded, desktop and high-performance computing domains. In all cases we will demonstrate the effectiveness of the proposed framework in exploiting the inherent parallelism of applications and enabling the runtime adaptation of the platforms to the changing needs of the applications.

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Section: Target Platforms and Experimentsmentioning

confidence: 99%

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration

Papadimitriou

Pilato

Pnevmatikatos

et al. 2012

2012 IEEE 15th International Conference on Computational Science and Engineering

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“…While the prototypes described in [Canis et al, 2013;Chung et al, 2012;Cong and Xiao, 2013;Ismail and Shannon, 2011;Lysecky and Vahid, 2009;Pilato et al, 2012;Vassiliadis et al, 2004;Willenberg and Chow, 2013] implement the host and the kernels on the same chip (embedded hardwired or soft processor as the host), the implementation of [Benini et al, 2012;Betkaoui et al, 2011;Convey Computer, 2012;Ling et al, 2009;Putnam et al, 2014;Schumacher et al, 2012;Stuecheli, 2013;Voros et al, 2013] uses different chips for the host and the kernels.…”

Section: Communication Infrastructurementioning

confidence: 99%

“…Please note that, almost all the embedded accelerator systems presented in Section 2.3 compare their systems against a host running at a low frequency, for example, 85MHz in [Lysecky and Vahid, 2009], 125MHz in [Ismail and Shannon, 2011], 100MHz in [Pilato et al, 2012], 75MHz in [Canis et al, 2013], etc., while the Molen system in this work is compared to a host running at 400MHz. Four applications are used for the following experiments.…”

Section: Performance Analysismentioning

confidence: 99%

“…• Bus-based interconnect: Molen [Vassiliadis et al, 2004], Warp processor [Lysecky and Vahid, 2009], IMORC [Schumacher et al, 2012], the target systems in [Canis et al, 2013;Ismail and Shannon, 2011;Pilato et al, 2012], and IBM's PowerEN use a bus as the communication infrastructure. In these systems, data is transferred between the main memory and the local memories of the kernels through the bus.…”

Section: Communication Infrastructurementioning

confidence: 99%

See 1 more Smart Citation

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

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