On the Behavior of Input Queuing Switch Architectures

Marsan, Marco Ajmone; Bianco, A.; Giaccone, Paolo; Leonardi, E.; Neri, F.; Filippi, E.

doi:10.1002/ett.4460100203

Cited by 30 publications

(17 citation statements)

References 13 publications

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“…Equation (1) means that at most one cell can arrive at each input during a time slot, while (2) means that at most one cell can be forwarded from each input. At most one cell can be re-enqueued into a queue, according to (3); this implies a memory access speedup equal to 2: at a given queue in each time slot at most one cell arrives and one cell is re-enqueued.…”

Section: A Switch Descriptionmentioning

confidence: 99%

“…Definition 1: A request set is said -complex, with 1 , if 1) cells are queued at each active input ; 2) cells are directed to each output ; 3) for each subset of comprising cells, a destination exists to which all the cells in the subset are directed. Table III reports an example of a 2-complex request set for a 6 6 switch, where only inputs and are active.…”

Section: -Complex Traffic Definitionmentioning

confidence: 99%

“…We consider both pure input-queued (IQ) architectures, where buffers reside only at input ports and no internal speedup is required, and combined input and output queued (CIOQ) architectures where buffers reside at both input and output ports, and a moderate internal speedup is provided in the switching fabric. The reason to focus on this class of switch architectures is that they are considered to be the most promising for the implementation of extremely fast packet switches and routers [1], thanks to the fact that the aggregate bandwidth required in their switching fabric does The authors are with the Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy (e-mail: ajmone@polito.it; bianco@polito.it; giaccone@polito.it; leonardi@polito.it; neri@polito.it).…”

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confidence: 99%

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Multicast traffic in input-queued switches: Optimal scheduling and maximum throughput

Marsan

Bianco

Giaccone

et al. 2003

IEEE/ACM Trans. Networking

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Abstract-This paper studies input-queued packet switches loaded with both unicast and multicast traffic. The packet switch architecture is assumed to comprise a switching fabric with multicast (and broadcast) capabilities, operating in a synchronous slotted fashion. Fixed-size data units, called cells, are transferred from each switch input to any set of outputs in one time slot, according to the decisions of the switch scheduler, that identifies at each time slot a set of nonconflicting cells, i.e., cells neither coming from the same input, nor directed to the same output.First, multicast traffic admissibility conditions are discussed, and a simple counterexample showing intrinsic performance losses of input-queued with respect to output-queued switch architectures is presented. Second, the optimal scheduling discipline to transfer multicast packets from inputs to outputs is defined. This discipline is rather complex, requires a queuing architecture that probably is not implementable, and does not guarantee in-sequence delivery of data. However, from the definition of the optimal multicast scheduling discipline, the formal characterization of the sustainable multicast traffic region naturally follows. Then, several theorems showing intrinsic performance losses of input-queued with respect to output-queued switch architectures are proved. In particular, we prove that, when using per multicast flow FIFO queueing architectures, the internal speedup that guarantees 100% throughput under admissible traffic grows with the number of switch ports.

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Section: A Switch Descriptionmentioning

confidence: 99%

Section: -Complex Traffic Definitionmentioning

confidence: 99%

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confidence: 99%

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Multicast traffic in input-queued switches: Optimal scheduling and maximum throughput

Marsan

Bianco

Giaccone

et al. 2003

IEEE/ACM Trans. Networking

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“…In [24], we proposed a general taxonomy for SAs. Any SA can be decomposed into two main components: 1) Metrics computation.…”

Section: B Considered Cell-mode Scheduling Algorithms (Cm-sas)mentioning

confidence: 99%

Packet-mode scheduling in input-queued cell-based switches

Marsan

Bianco

Giaccone

et al. 2002

IEEE/ACM Trans. Networking

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Abstract-We consider input-queued switch architectures dealing at their interfaces with variable-size packets, but internally operating on fixed-size cells. Packets are segmented into cells at input ports, transferred through the switching fabric, and reassembled at output ports. Cell transfers are controlled by a scheduling algorithm, which operates in packet-mode: all cells belonging to the same packet are transferred from inputs to outputs without interruption. We prove that input-queued switches using packet-mode scheduling can achieve 100% throughput, and we show by simulation that, depending on the packet size distribution, packet-mode scheduling may provide advantages over cell-mode scheduling.Index Terms-Input queued switched, packet switching, scheduling algorithms, variable size packets.

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“…But they do not guarantee delay bounds for each packet. Many practical scheduling algorithms [9,10] have been proposed to approximate MWM performance. Their simplicity usually leads to some performance penalties, usually in the form of throughput degradation and/or larger delays.…”

Section: Introductionmentioning

confidence: 99%