On the Complexity of Cache Analysis for Different Replacement Policies

Abstract

Modern processors use cache memory: a memory access that "hits" the cache returns early, while a "miss" takes more time. Given a memory access in a program, cache analysis consists in deciding whether this access is always a hit, always a miss, or is a hit or a miss depending on execution. Such an analysis is of high importance for bounding the worst-case execution time of safety-critical real-time programs.There exist multiple possible policies for evicting old data from the cache when new data are brought in, and different policies, though apparently similar in goals and performance, may be very different from the analysis point of view. In this paper, we explore these differences from a complexity-theoretical point of view. Specifically, we show that, among the common replacement policies, LRU (Least Recently Used) is the only one whose analysis is NP-complete, whereas the analysis problems for the other policies are PSPACE-complete.

The complexity gap in the static analysis of cache accesses grows if procedure calls are added

“…Monniaux and Touzeau [13,Lemma 20] show: Lemma 2. The reachability problem for Boolean register machines is PSPACEcomplete.…”

“…In [13], the proofs that the exist-hit and exist-miss problems for controlflow graphs adorned with cache accesses under the LRU policy could be solved in NP relied on path compression: if there exists an execution of arbitrary length that reaches a control location l with a in the cache (respectively, not in the cache), then there exists one of polynomial length with the same property, which is the NP witness. More specifically, the proof relied on the possibility to "compress" an execution path between two control locations into a path of polynomial length with the same set of control edges along the two paths, using classical arguments such as "if the length of an execution exceeds the number of states, then it encounters the same state twice".…”

“…Definition 2. A Boolean register machine [13] is defined by a number r of registers and a directed (multi)graph with an initial node and a final node, with edges adorned by instructions of the form:…”

“…If the control-flow graph is acyclic, similar reasoning leads to membership in NP. Monniaux and Touzeau [13], considering the LRU, PLRU, NMRU and FIFO policies, showed, in addition, that:…”

“…To summarize, for all policies, the analysis problems are NP-complete for acyclic control-flow graphs, but there is a gap between LRU (NP-complete) and the others (PSPACE-complete) for general control-flow graphs. Monniaux and Touzeau [13] however left to future work the question of adding procedure calls (pushdown control) to the setting.…”