On the Design Flow of the Fractional-Order Analog Filters Between FPAA Implementation and Circuit Realization

Hassanein, Ahmed M. D. E.; Madian, Ahmed H.; Radwan, Ahmed G.; Said, Lobna A.

doi:10.1109/access.2023.3260093

Cited by 12 publications

(2 citation statements)

References 64 publications

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“…(b) Employing a Field Programmable Analog Array (FPAA) device, such as the Anadigm AN231E04 device [35,36], where programmability is achieved through the utilization of the switched-capacitor technique. For this purpose, the transfer function in ( 26) is alternatively expressed as a sum of high-pass, band-pass, and low-pass biquad filters…”

Section: Implementations Of the Power-law Bilinear Negative Group Del...mentioning

confidence: 99%

Power-Law Negative Group Delay Filters

Nako,

Psychalinos,

Elwakil

et al. 2024

Electronics

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A study of the behavior of the power-law negative group delay filters, accompanied by a comparison with their integer-order counterparts, is performed in this work. Employing a curve-fitting based approximation technique, the resulting integer-order rational transfer function is versatile in the sense that it has the same form independent of the order and/or the type of the filter. Its implementation is performed by following three alternative approaches, each one offering different advantages. The findings of this work are supported by simulation and experimental results using suitable platforms.

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Section: Implementations Of the Power-law Bilinear Negative Group Del...mentioning

confidence: 99%

Power-Law Negative Group Delay Filters

Nako,

Psychalinos,

Elwakil

et al. 2024

Electronics

View full text Add to dashboard Cite

show abstract

“…With respect to the former, Charef's approximation of the FO operator has been implemented in, e.g., [10][11][12]. For analog FO filters, the realization of the operator using partial fraction expansion (PFE), Oustaloup's (in its classical and modified versions), Matsuda's, and Charef's methods can be found in [13]. Likewise, an implementation based on Oustaloup's approximation combined with a curve-fitting-based method has been proposed in [14] for power-law filters (transfer functions raised to an FO) and using particle swarm optimization in [15].…”

Section: Introductionmentioning

confidence: 99%

Field-Programmable Analog Array Implementation of Neuromorphic Silicon Neurons with Fractional Dynamics

Serrano-Balbontín,

Tejado,

Vinagre

2024

Fractal Fract

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Silicon neurons are bioinspired circuits with the capability to reproduce the modulation through pulse-frequency observed in real neurons. They are of particular interest in closed-loop schemes to encode the control signal into pulses. This paper proposes the analog realization of neuromorphic silicon neurons with fractional dynamics. In particular, the fractional-order (FO) operator is introduced into classical neurons with the intention of reproducing the adaptation that has been observed experimentally in real neurons, which is the variation in the firing frequency even when considering a constant or periodic incoming stimulus. For validation purposes, simulations using a field-programmable analog array (FPAA) are performed to verify the behavior of the circuits.

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Performance analysis of fractional‐order modified SRF PLL under grid abnormalities

Devi,

Singh

2024

Circuit Theory & Apps

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This article proposes two different structures of fractional‐order modified synchronous reference frame phase‐locked loop (MSRF PLL) and discusses their performance under different grid abnormalities. Phase‐locked loop (PLL) is a type of closed‐loop feedback control system that ensures phase and frequency coherence between its input and output signals. The basic synchronous reference frame phase‐locked loop (SRF‐PLL) is a conventional synchronization technique that is frequently employed in grid‐connected systems for power electronic converters. The SRF‐PLL offers rapid and precise phase/frequency detection under ideal grid environments. However, its performance is severely hampered under unbalanced and distorted grid environments. This paper discusses two new configurations of fractional‐order (FO) modified SRF (MSRF), one with fractional order only in additional low‐pass filter of first order (FO‐LP) and another fractional order in both first‐order low‐pass filter and PI (FO‐LPFO‐PI) of MSRF. These controllers are assembled using FOs “a” and “b” with limits as 0 < a < 2 and 0 < b < 2. The performance analysis of proposed FO MSRFs is done under grid abnormalities like voltage sag and swell, polluted grid supply, frequency change, phase change, and variables for dc offset. The outcomes of simulation are acquired using FO modeling and control (FOMCON) toolbox for MATLAB/SIMULINK, and the experimental results are validated with simulation results. A fair comparison among the MSRF‐PLL, FO‐LP MSRF‐PLL, and FO‐LPFO‐PI MSRF‐PLL is also depicted during grid abnormalities.

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On the Design Flow of the Fractional-Order Analog Filters Between FPAA Implementation and Circuit Realization

Cited by 12 publications

References 64 publications

Power-Law Negative Group Delay Filters

Power-Law Negative Group Delay Filters

Field-Programmable Analog Array Implementation of Neuromorphic Silicon Neurons with Fractional Dynamics

Performance analysis of fractional‐order modified SRF PLL under grid abnormalities

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