On the design of a highly testable cell library

Saraiva, M.; Santos, M.B.; Casimiro, António; Teixeira, Isabel Maria Cacho; Teixeira, J.P.

doi:10.1016/0165-6074(92)90343-6

Cited by 4 publications

(1 citation statement)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…At present, the test view of a testable cell library, IdLib10 [23] has been characterised. In Table 1, fault simulation results and simulator performance data is shown for several ISCAS benchmark [24,25] circuits.…”

Section: Resultsmentioning

confidence: 99%

Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

Santos

Teixeira

1999

Proceedings of the Conference on Design, Automation and Test in Europe

View full text Add to dashboard Cite

The validation of high-quality tests requires DefectOriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO fault simulation, using HDL. A novel tool, veriDOFS, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults. Design hierarchy is exploited, by pre-computing a test view of each cell in a library. The good trade-off accuracy / tractability, as well as the computational efficiency of the new tool are demonstrated by means of structural benchmarks up to 100,000 transistors and 300,000 realistic faults.

show abstract

Section: Resultsmentioning

confidence: 99%

Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

Santos

Teixeira

1999

Proceedings of the Conference on Design, Automation and Test in Europe

View full text Add to dashboard Cite

show abstract

Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

Santos¹,

Teixeira²

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

View full text Add to dashboard Cite

The validation of high-quality tests requires Defect-Oriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO fault simulation, using HDL. A novel tool, veriDOFS, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults. Design hierarchy is exploited, by pre-computing a test view of each cell in a library. The good trade-off accuracy / tractability, as well as the computational efficiency of the new tool are demonstrated by means of structural benchmarks up to 100,000 transistors and 300,000 realistic faults.

show abstract