On the design of a reliable current reference for systems‐on‐chip

Abstract

Modern systems‐on‐chip use multiple current references to guarantee appropriate circuit biasing according to the required performance and power consumption. New reference topologies have emerged due to the necessity of ultra‐low‐power systems. Still, in the micro‐Ampere domain, the most common architectures are preferred in industry‐based applications, due to their reliability and accuracy. Motivated by the limited documentation and data associated with current references for SoCs, this work presents key observations in the design decisions, based on error contributions from the inherent elements of a reliable voltage‐to‐current reference architecture. Monte Carlo simulations show results for a 5 μA current reference, with inaccuracies at ±3σ of ±4% and ±1.3%, without and with trimming, respectively. Furthermore, two current references were fabricated using a 0.18 μm CMOS standard technology, in two different SoCs. Measurement results across voltage and temperature variations showed results for 50 μA ± 0.24% and 5 μA ± 0.8% current references without trimming.