On the design of an offset-PLL modulation loop for the EGSM band

Hafez, A.; Aboueldahab, W.F.; Helmy, A.

doi:10.1109/iscas.2004.1328963

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Cited by 2 publications

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“…4. The value of C 1 can be calculated from the equation (1) and R can be found through equation (2). C 2 is approximately one tenth of C 1 .…”

Section: Loop Filtermentioning

confidence: 99%

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A Fully Differential 24GHz Transmit PLL in a 0.13μm CMOS Technology

Shang

Rogers

Chiu

2006

2006 IEEE North-East Workshop on Circuits and Systems

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This paper describes the design of a transmit PLL circuit at 24GHz in a 0.13µm CMOS technology. This transmit PLL is made with fully differential circuits to reject common mode noise. The VCO output frequency is 24GHz and the IF frequency is 400 MHz. In order to take advantage of the fully differential VCO, a differential charge pump and loop filter are developed. This differential charge pump draws no DC current when PLL is in lock. The supply voltage for this PLL is 1.5V. The loop bandwidth is 500 KHz and the in band phase noise at 100 KHz offset is -112dBc. The settling time is 220 ns.

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“…4. The value of C 1 can be calculated from the equation (1) and R can be found through equation (2). C 2 is approximately one tenth of C 1 .…”

Section: Loop Filtermentioning

confidence: 99%

“…In an application where constant-envelop modulation is used, transmitters based on a transmit PLL are widely used [2]. The transmitter-PLL block diagram is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%